
114
CHAPTER 3 CPU
r Changing to normal state (RUN) and reset
r Changing to/wake-up from standby mode
STBC: Standby control register
Table 3.7-7 Changing to Main Clock Mode Run State and Reset (One-Clock Option)
State transition
Conditions/events required to transition
Products with power-on reset
(Figure 3.7-4 "State Transition Diagram
3 (Products with Power-on Reset)")
Products without power-on reset
(Figure 3.7-5 "State Transition
Diagram 3 (Products without Power-
on Reset)")
Changing to normal
state (RUN) after
power-on
[1]
[2]
Main clock oscillation stabilization
delay time complete. (Timebase
timer ouptput.)
Wake-up from Reset input.
[1]
[2]
External reset input must be
held asserted until main clock
oscillation has had time to
stabilize.
Reset in RUN state
[3]
Have external, software, or watchdog
reset.
[3]
Have external, software, or
watchdog reset.
Table 3.7-8 Changing to/wake-up from Standby Modes (Options: Power-on Reset, Two Clocks)
State transition
Conditions/events required to transition
Products with power-on reset
(Figure 3.7-4 "State Transition Diagram
3 (Products with Power-on Reset)")
Products without power-on reset
(Figure 3.7-5 "State Transition
Diagram 3 (Products without Power-
on Reset)")
Changing to sleep
mode
[1]
STBC: SLP = 1
[1]
STBC: SLP = 1
Wake-up from
sleep mode
[2]
[3]
Interrupt
External reset
[2]
[3]
Interrupt
External reset
Changing to stop
mode
[4]
STBC: STP = 1
[4]
STBC: STP = 1
Wake-up from stop
mode
[5]
[6]
[7]
[8]
External interrupt
Main clock oscillation stabilization
delay time complete. (Timebase
timer output.)
External reset
External reset (during oscillation
stabilization delay time)
[5]
[6]
[7]
[8]
External interrupt
Main clock oscillation
stabilization delay time
complete. (Timebase timer
output.)
External reset
External reset (during oscillation
stabilization delay time)