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CHAPTER 3 CPU
r Power-on reset
Products can be set to with or without power-on reset (optional). On products with power-on
reset, turning on the power generates a reset. The reset operation is performed after the
oscillation stabilization delay time has passed.
On products without power-on reset, an external reset circuit is required to generate a reset
when the power is turned on.
s Main Clock Oscillation Stabilization Delay Time and the Reset Source
Whether there will be an oscillation stabilization delay time depends on the operating mode
when reset occurs, and the power-on reset option selected.
Following reset, operation always starts out in the normal main clock operating mode,
regardless of the kind of reset it was, or the operating mode (the clock mode and standby mode)
prior to reset. Therefore, if reset occurs while the main clock oscillator is stopped or in a
stabilization delay time, the system will be in a "main clock oscillation stabilization reset" state,
and a clock stabilization period will be provided. If the device is set for no power-on reset,
however, no main clock oscillation stabilization delay time is provided for power-on or external
reset.
In software or watchdog reset, if the reset occurs while the device is in main clock mode, no
stabilization time is provided. If it occurs in the subclock mode, however, a stabilization time is
provided since the main clock oscillation is stopped.
Table 3.5-2 "Reset Source and Oscillation Stabilization Delay Time" shows the relationships
between the reset sources and the main clock oscillation stabilization delay time, and reset
mode (mode fetch) operations.
Table 3.5-2 Reset Source and Oscillation Stabilization Delay Time
Reset source
Operating
state
Reset operation and main clock oscillation stabilization delay time
With power-on reset
Without power-on reset
External
reset*1
At power on,
during stop
mode, or
subclock mode
After the main clock oscillation
stabilization delay time, if the external
reset is waked up, reset is operated.*2
Reset state is held until
external reset is waked up;
then the reset is operated.
Software and
watchdog reset
Main clock
mode
After 4-instruction-cycle reset occurs, reset is operated.*3
Subclock mode
Reset is operated after the main clock oscillation stabilization delay
time.*2
Power-on reset
Device enters main clock oscillation
stabilization delay time at power on.
Reset is operated after delay time
ends.*2
An external circuit must be
provided to hold external reset
asserted at power on until main
clock has had time to stabilize.
*1:
No oscillation stabilization delay time is required for external reset while main clock mode is operating.
Reset is operated after external reset is waked up.
*2:
If the reset output option is selected, "L" is output at RST pin during the main clock oscillation
stabilization delay time.
*3:
If the reset output option is selected, "L" level is output at RST pin during 4-instruction-cycle.