- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69019 > MB89P965PFM 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP48 PDF資料下載
參數(shù)資料
| 型號： | MB89P965PFM |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-48 |
| 文件頁數(shù)： | 170/278頁 |
| 文件大小： | 1847K |
| 代理商： | MB89P965PFM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁當前第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁
MB89960 series
CHAPTER 12 I2C Interface
229
12
Besides the above two situations, writing IBCR: MSS = “1” or IBCR: SCC = “1” do not generate
any START condition. Moreover, during the bus is used by other master device in the system,
IBSR: AL bit is set when IBCR: MSS is written “1”.
s Addressing
In master mode, after the START condition is generated, IBSR: BB and IBSR: TRX is set. The
slave address stored in IDAR register (bit 7 to bit 1) is sent out with MSB first. This is a seven
bits long calling address followed by a R/W bit (bit 0 of IDAR). The R/W bit tells the slave the
desired direction of data transfer.
After the slave address is transferred, an acknowledge bit is received. An acknowledge bit is
signaled from the receiving device by pulling the SDA line LOW at the 9th clock. (See Figure
12.5a) Then the R/W bit (bit 0 of IDAR) is logically reversed and put into IBSR: TRX.
In slave mode, after the START condition is detected, IBSR: BB = “1” and IBSR: TRX = “0” is
set. The received data from master is stored into IDAR register and compared with its own
specific address stored in IADR. When they are matched, IBSR: AAS is set and an
acknowledge bit is sent to the master. Then the bit 0 of the received data (bit 0 of IDAR) is put
into IBSR: TRX.
s Data Transfer
Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a
direction specified by the R/W bit sent by the calling master.
Each data byte is 8 bit long. Data can be changed only during SCL line is LOW and must be
held stable during SCL is HIGH as shown in Figure 12.5a. One clock pulse is for one bit data
transferring, MSB is transferred first. Each byte data has to be followed by an acknowledge bit,
which signaled from the receiving device by pulling the SDA line LOW at the 9th clock. So one
complete data byte transferring needs 9 clock pulses.
s Acknowledge
The acknowledge bit is sent from the receiver to the transmitter at the 9th clock in data byte
transfer.
In the receiver, the transmission of acknowledge bit can be enabled (IBCR: ACK = “1”) or
disabled (IBCR: ACK = “0”) by setting the bus control register. In the transmitter, the
acknowledge bit is detected and stored in IBSR: LRB.
When the master receiver does not acknowledge the slave transmitter after one byte
transmission, the IBSR: TRX in slave device is cleared and slave receive mode is set. So that
the slave releases the SDA line for the master to generate STOP or repeated START condition.
s STOP condition
The master can terminate the communication by generating a STOP condition to free the bus.
However, the master may generate a START condition followed by a calling command without
generating a STOP condition first. This is called repeated START condition. A STOP condition
is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH.
When the bus master device goes into interrupt subroutine (IBCR: MSS = “1”, IBSR: BB = “1”,
IBCR: INT = “1” and IBSR: AL = “0”), IBCR: MSS is written “0” to generate the STOP condition
and then the device is changed to slave mode.
Besides the above situation, writing IBCR: MSS = “0” do not generate any STOP condition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB89965PF-G-XXX | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP48 |
| MB89965PFM-G-XXX | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP48 |
| MB89965PFV-G-XXX | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| MB89P965PFV | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| MB89F202RAPFV-GE1 | 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDSO34 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB89P980 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89P985 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89P985-PFM-101 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89P985-PFM-201 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89P985PFV-101 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復。