viii
3.7.7
State Transition Diagram 2 (Options: No Power-on Reset, Two Clocks) .................................... 110
3.7.8
State Transition Diagram 3 (One-clock Option) ........................................................................... 113
3.7.9
Notes on Using Standby Modes .................................................................................................. 115
3.8
Memory Access Mode ...................................................................................................................... 117
CHAPTER 4
I/O PORTS ................................................................................................ 119
4.1
Overview of I/O Ports ........................................................................................................................ 120
4.2
Port 0 and Port 1 ............................................................................................................................... 123
4.2.1
Port-0 and Port-1 Registers (PDR0, PDR1, PURR0 DDR0, DDR1, PURR1) .............................. 127
4.2.2
Operation of Port 0 and Port 1 ..................................................................................................... 130
4.3
Port 2 ................................................................................................................................................ 132
4.3.1
Port-2 Registers (PDR2, DDR2) .................................................................................................. 136
4.3.2
Operation of Port 2 ..................................................................................................................... 138
4.4
Port 3 ................................................................................................................................................ 140
4.4.1
Port-3 Register (PDR3) ................................................................................................................ 142
4.4.2
Operation of Port 3 ..................................................................................................................... 143
4.5
Ports 4, 6 and 7 ................................................................................................................................. 145
4.5.1
Port-4, Port-6, and Port-7 Registers (PDR4, PDR6, and PDR7) ................................................. 148
4.5.2
Operation of Port 4, Port 6 and Port 7 ......................................................................................... 150
4.6
Port 5 ............................................................................................................................................... 152
4.6.1
Port-5 Register (PDR5) ................................................................................................................ 155
4.6.2
Operation of Port 5 ...................................................................................................................... 157
4.7
Program Example for I/O Ports ......................................................................................................... 158
CHAPTER 5
TIMEBASE TIMER .................................................................................... 161
5.1
Overview of Timebase Timer ........................................................................................................... 162
5.2
Block Diagram of Timebase Timer .................................................................................................... 164
5.3
Timebase Timer Control Register (TBTC) ........................................................................................ 166
5.4
Timebase Timer Interrupt .................................................................................................................. 168
5.5
Operation of Timebase Timer ........................................................................................................... 169
5.6
Notes on Using Timebase Timer ...................................................................................................... 171
5.7
Program Example for Timebase Timer ............................................................................................. 173
CHAPTER 6
WATCHDOG TIMER ................................................................................. 175
6.1
Overview of Watchdog Timer ............................................................................................................ 176
6.2
Block Diagram of Watchdog Timer ................................................................................................... 177
6.3
Watchdog Timer Control Register (WDTC) ...................................................................................... 179
6.4
Operation of Watchdog Timer ........................................................................................................... 181
6.5
Notes on Using Watchdog Timer ...................................................................................................... 183
6.6
Program Example for Watchdog Timer ............................................................................................. 184
CHAPTER 7
8-BIT PWM TIMER .................................................................................... 185
7.1
Overview of 8-bit PWM Timer ........................................................................................................... 186
7.2
Block Diagram of 8-bit PWM Timer ................................................................................................... 189
7.3
Structure of 8-bit PWM Timer 1 ........................................................................................................ 191
7.3.1
PWM1 Control Register (CNTR1) ................................................................................................ 193
7.3.2
PWM 1 Compare Register (COMR1) ........................................................................................... 195
7.4
Structure of 8-bit PWM Timer 2 ........................................................................................................ 197