參數(shù)資料
型號: MB89635RP-SH
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP64
封裝: SHRINK, DIP-64
文件頁數(shù): 115/153頁
文件大?。?/td> 7326K
代理商: MB89635RP-SH
HARDWARE CONFIGURATION
2-41
(b) Control register 2 (CNTR2)
[Bit 7] TPE1: Counter-operation enable bit
[Bit 6] TPE2: Counter-operation enable bit
When this bit is set to 1, the timer or PWM-control circuit starts operation.
[bit 4] CK12: CH2 input-clock switching bit
When 1 is written at this bit, CH1 toggle output is selected as the input clock of CH2 irrespective of the
values of the SC21 and SC20 bits.
Do not write 1 at this bit when the CH1-2PWM mode is set (CH1-2 bit = 1).
[Bit 3] TIR1: CH1 interrupt-request flag bit
[Bit 2] TIR2: CH2 interrupt-request flag bit
When an interrupt source occurs, these bits go to 1. To clear the generated interrupt source, write 0 at
these bits. The meaning of each bit to be read is as follows:
Note that 1 is always read when the Read Modify Write instruction is read.
The meaning of each bit to be written is as follows:
Note: In the PWM operation mode, neither the read nor write values of these bits have any meaning.
[Bit 1] TIE1: CH1 interrupt enable bit (timer mode)
[Bit 0] TIE1: CH2 interrupt enable bit (timer mode)
If these bits are set to 1, an interrupt occurs when the values of the counter and compare register agree.
However, in the PWM operation mode, interrupt occur irrespective of the values of these bits.
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