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參數(shù)資料
| 型號(hào)： | MB89615RPFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CFP -55 to 125 |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, PLASTIC, SQFP-64 |
| 文件頁(yè)數(shù)： | 27/44頁(yè) |
| 文件大?。?/td> | 665K |
| 代理商： | MB89615RPFV |
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27
MB89610R Series
(6) Bus Read Timing
(V
CC
= +5.0 V
±
10%, F
C
= 10 MHz, V
SS
= 0.0 V, T
A
= –40
°
C to +85
°
C)
Value
* :For information on t
inst
, see “(4), Instruction Cycle.”
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min.
Max.
Valid address
→
RD
↓
time
t
AVRL
RD, A15 to 08
AD7 to 0
—
1/4 t
inst*
– 64 ns
—
μ
s
RD pulse width
Valid address
→
read
data time
RD
↓
→
read data time t
RLDV
RD
↑ →
data hold time t
RHDX
RD
↑ →
ALE
↑
time
RD
↑ →
address
invalid time
RD
↓ →
CLK
↑
time
CLK
↓
→
RD
↑
time
RD
↓
→
BUFC
↓
time
BUFC
↑ →
valid
address time
t
RLRH
RD
1/2 t
inst*
– 20 ns
—
μ
s
t
AVDV
AD7 to 0,
A15 to 08
—
1/2 t
inst*
μ
s
No wait
RD, AD7 to 0
—
1/2 t
inst*
– 80 ns
μ
s
ns
μ
s
No wait
AD7 to 0, RD
0
—
t
RHLH
RD, ALE
1/4 t
inst*
– 40 ns
—
t
RHAX
RD, A15 to 08
1/4 t
inst*
– 40 ns
—
μ
s
t
RLCH
RD, CLK
1/4 t
inst*
– 40 ns
—
μ
s
ns
μ
s
t
CLRH
0
—
t
RLBL
RD, BUFC
–5
—
t
BHAV
A15 to 08,
AD7 to 0, BUFC
5
—
μ
s
ALE
AD
A
RD
BUFC
CLK
2.4
V
0.8
V
0.8
V
2.4
V
0.8
V
0.7
V
CC
0.3
V
CC
0.7
V
CC
0.3
V
CC
2.4
V
0.8
V
2.4
V
0.8
V
0.8
V
2.4
V
0.8
V
2.4
V
0.8
V
2.4
V
2.4
V
0.8
V
t
RHDX
t
RHAV
t
RLBL
t
CLRH
t
RHLH
t
RLRH
t
RLDV
t
AVRL
t
RHAX
t
RLCH
t
AVDV
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