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參數(shù)資料
| 型號： | MB89530A |
| 廠商： | Fujitsu Limited |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 27/69頁 |
| 文件大?。?/td> | 1206K |
| 代理商： | MB89530A |
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MB89530A Series
27
The RP register shows the address of the register bank currently being used, so that the RP value and the actual
address are related by the conversion rule shown in the following illustration.
The CCR register has bits that show the content of results of calculations and transferred data, and bits that
control CPU operation during interrupts.
In addition, the following general purpose registers are available.
General purpose registers: 8 bits length, used to contain data.
The general purpose registers are 8-bit registers located in memory. There are eight such registers per bank,
and the MB89530A series have up to 32 banks for use. The bank currently in use is indicated by the register
bank pointer (RP).
H-flag
: Set to “1” if calculations result in carry or borrow operations from bit 3 to bit 4, otherwise set to “0”.
This flag is used for decimal correction instructions.
: This flag is set to “1” if interrupts are enabled, and “0” if interrupts are prohibited.
The default value at reset is “0”.
: Indicates the level of the currently permitted interrupts.
Only interrupt requests having a more powerful level than the value of these bits will be processed.
I-flag
IL1, 0
IL1
IL0
Interrupt level
Strength
0
0
1
Strong
Weak
0
1
1
0
2
1
1
3
N-flag
Z-flag
V-flag
C-flag
: Set to “1” if the highest bit is “1” after a calculation, otherwise cleared to “0”.
: Set to “1” if a calculation result is “0”, otherwise cleared to “0”.
: Set to “1” if a two’s complement overflow results during a calculation, otherwise cleared to “0”.
: Set to “1” if a calculation results in a carry or borrow operation from bit 7, otherwise cleared to “0”.
This is also the shift-out value in a shift instruction.
General purpose register area real address conversion principle
"0"
"0"
"0"
"0"
"0"
"0"
"0"
"1"
R4
R
3
R2
R1
R0
b
2
b
1
b
0
A7
A6
A5
A4
A
3
A2
A1
A0
A15
A14 A1
3
A12 A11 A10
A9
A
8
Address
generated
RP upper
Operation code
lower
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