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參數(shù)資料
| 型號： | MB89170 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Replaced by SN54LS03 : Quadruple 2-Input Positive-NAND Buffers With Open-Collect 20-LCCC -55 to 125 |
| 中文描述： | 8位微控制器專有 |
| 文件頁數(shù)： | 41/50頁 |
| 文件大?。?/td> | 626K |
| 代理商： | MB89170 |
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41
MB89170/170A/170L Series
I
INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very
×
is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Indicates that the contents of
×
is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of
×
is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
(
×
)
((
×
))
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相關(guān)代理商/技術(shù)參數(shù) |
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