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參數(shù)資料
| 型號： | MB88R157A |
| 廠商： | FUJITSU LTD |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 4.40 X 3.10 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 1186K |
| 代理商： | MB88R157A |
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MB88R157A
DS04-29146-1E
17
AC characteristics (1)
(Ta
= 20 °C to + 85 °C, VDD = 3.3 V ± 0.3 V)
(Continued)
Parameter
Sym-
bol
Pin
name
Conditions
Value
Unit
Min
Max
Crystal oscillation
frequency
fx
XIN,
XOUT
Fundamental oscillation
10
40
MHz
3rd over-tone
40
48
Input frequency
fin
XIN
10
50
MHz
Internal oscillation
frequency
fVCO
20
134
MHz
Output frequency
fOUT
OUT
1
134
MHz
Output slewing
rate*2
SR
Slewing rate low,
Driving ability small,
Load capacitance 15pF
0.44
V/ns
Slewing rate high,
Driving ability small,
Load capacitance 15pF
0.47
Slewing rate low,
Driving ability large,
Load capacitance 15pF
0.79
Slewing rate high,
Driving ability large,
Load capacitance 15pF
0.90
Output impedance
ZO
Driving ability small
58
Ω
Driving ability large
29
Output clock duty
cycle
tDCC
VCO clock output
40
60
%
tDCR
At reference clock output
TDCI
10*1
TDCI
+ 10*1
Modulation
frequency
(number of input
clocks per one
modulation)
FMOD
(NMOD)
fin/(448
×
(L
+ 1))
(448
×
(L
+ 1))
fin/(532
×
(L
+ 1))
(532
×
(L
+ 1))
fin/(616
×
(L
+ 1))
(616
×
(L
+ 1))
kHz
(clks)
Power supply time
tR
VDD
0.2 V to 3.0 V
0.05
20
ms
Lock-up time
tLK
OUT
At power on
SSCG mode
400/fin+6
TBD
ms
PLL mode
400/fin+2
TBD
At power
down release
SSCG mode
7TBD
PLL mode
3TBD
Cycle-cycle jitter
tJC
No load
capacitance
fOUT
≥ 3 MHz
TBD
ps-
rms
fOUT < 3 MHz
TBD
Output stop time
from OE exit.
tOD
ta
= 1/ fOUT
2
× ta
ns
Output start time
after OE entry
tOE
ta
= 1/ fOUT
2
× ta
ns
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