參數(shù)資料
型號(hào): MB88141PFV
廠商: FUJITSU LTD
元件分類: DAC
英文描述: D/A Converter for Digital Tuning (With Built-in OP Amp and I/O Expander)
中文描述: SERIAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24
封裝: PLASTIC, SSOP-24
文件頁數(shù): 14/20頁
文件大?。?/td> 250K
代理商: MB88141PFV
MB88141
14
2.
AC Characteristics
*3: The I/O expander input open time value applies to read operation following an I/O write operation, or to an
I/O write operation following a read operation.
Parameter
Symbol
Con-
dition
Value
Unit
Standard mode
High speed mode
Min.
Max.
Min.
Max.
SCL clock frequency
f
SCL
0
100
0
400
kHz
Bus free time between “stop” condition
and “start” condition
t
BUF
4.7
1.3
μ
s
Hold time (resend) “start” condition.
The first clock pulse is generated after
this interval.
t
HD ; STA
4.0
0.6
μ
s
SCL clock low hold time
t
LOW
4.7
1.3
0.9
300
μ
s
μ
s
μ
s
μ
s
ns
SCL clock high hold time
t
HIGH
4.0
0.6
Resend “start” condition setup time
t
SU ; STA
4.7
0.6
Data hold time
t
HD ; DAT
0
0
Data setup time
t
SU ; DAT
250
4.0
100
SDA and SCL signal fall time
t
R
1000
20
+
0.1 Cb
20
+
0.1 Cb
0.6
ns
SDA and SCL signal rise time
t
F
300
300
ns
μ
s
“Stop” condition setup time
t
SU ; STO
Pulse width of spike suppressed by input
filter
t
SP
0
50
ns
Output fall time when
bus capacitance is
between 10 pF and
400 pF
Sink current 3 mA
t
OF
250
20
+
0.1 Cb
250
ns
Sink current 6 mA
20
+
0.1 Cb
250
ns
I
2
C bus line capacitance load
Cb
*1
200
400
200
400
pF
μ
s
ns
D/A
Analog output settling time
t
DL ; AO
100
100
I/O
expander
Digital output delay time
t
DL ; DO
*2
300
300
Input open time
t
DZ ; DI
*3
ns
Digital input setup time
t
SU ; DI
250
100
ns
μ
s
Digital input hold time
t
HD ; DI
0.9
0.9
*1: Load condition 1
*2: Load condition 2
C
AL
=
50 pF
Measurement point
R
AL
=
10 k
DUT
C
AL
=
50 pF
Measurement point
DUT
相關(guān)PDF資料
PDF描述
MB88141 D/A Converter for Digital Tuning (With Built-in OP Amp and I/O Expander)
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