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參數(shù)資料
| 型號： | MB86977PFV-G-BND |
| 廠商： | FUJITSU LTD |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | IP PACKET FORWARDING ENGINE |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, LQFP-208 |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 149K |
| 代理商： | MB86977PFV-G-BND |
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MB86977
9
I
BLOCK DESCRIPTION
1.
MAC block
The MAC block transmits and receives packets through the RMII or MII Interfaces, and performs Layer 2 (MAC)
functions as defined in IEEE 802.3. The MAC block transfers the received frames to the switch block, and
transmits frames received from the switch block to the output interface.
2.
SMI block
The SMI Block gathers various information (such as Full/Half Duplex, Link Status,10/100 Base, etc.) by reading
the PHY device registers through the SMI Interface, and configures the PHY device by writing through the SMI
Interface.
3.
Switch block
The Switch block stores packets received from the MAC block in RAMs (PRAM) , and transfers the packets to
the destination interface based on the information acquired from the Lookup block.
4.
Lookup block
The Lookup block looks up the MAC Address of the packet received from the MAC block, and returns destination
interface information to the switch block.
5.
Classifier block
The classifier block is used to determine the priority of the packets to be transferred between the WAN and
D.M.Z. ports. The packets can be classified into two priorities (high or low) by the classifier block. Packets
classified as high are placed in the high priority queue, and are processed by the switch block before the low
priority packets.
6.
Host interface block
The Host Interface block contains the FEF Engine and other minor blocks. The FEF Engine forwards packets
between interfaces and transmits packets to/from the host. The Host Interface is also used to read/write from/
to the internal registers. When the MB86977 receives packets destined for the host, the host interface asserts
an interrupt signal and specifies the information in the status register. The host transmits packets by writing a
descriptor to an internal register with the information necessary to transmit.
The host interface block has two 3K Byte integrated dual port RAMs that can be randomly accessed for trans-
mitting and receiving packets. The host interface can be accessed like a General-purpose SRAM.
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相關(guān)代理商/技術(shù)參數(shù) |
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