參數(shù)資料
型號(hào)： MB86960
廠商： Fujitsu Limited
英文描述： NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)
中文描述： 網(wǎng)絡(luò)接口控制器的編碼/解碼器（尼斯）
文件頁數(shù)： 27/65頁
文件大?。?/td> 488K
代理商： MB86960
MB86960
Table 9. DLCR4 — Transmit Mode Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
COL
CTR 3
R
1
COLLISION COUNT 3:
DLCR4<7:4> plus 1 ndicates the number of consecutive collisions
encountered by the current transmit packet. (Read only). See Table 10.
6
COL
CTR 2
R
1
COLLISION COUNT 2:
DLCR4<7:4> plus 1 ndicates the number of consecutive collisions
encountered by the current transmit packet. (Read only). See Table 10.
5
COL
CTR 1
R
1
COLLISION COUNT 1:
DLCR4<7:4> plus 1 ndicates the number of consecutive collisions
encountered by the current transmit packet. (Read only). See Table 10.
4
COL
CTR 0
R
1
COLLISION COUNT 0:
DLCR4<7:4> plus 1 ndicates the number of consecutive collisions
encountered by the current transmit packet. (Read only). See Table 10
3
0
N
0
REVERSED:
Write 0.
2
CNTRL
R
W
1
CONTROL OUTPUT:
The inverse of this is bit is output for general use on pin 95.
1
LBC
R
W
1
LOOPBACK CONTROL:
This bit controls the loopback function of the NICE
encoder/decoder. A 0 in this bit places the chip in internal loopback mode.
0
EN TX
DEFER
R
W
0
ENABLE TRANSMIT DEFER:
Program this bit low for normal network operation. When
high, the transmitter will not defer to traffic on the network.
Table 10. Collision Count
Collision
Count
16 COL
DLCR0<1>
DLCR4<7>
DLCR4<6>
DLCR4<5>
DLCR4<4>
COL
DLCR0<2>
0
0
0
0
0
0
0
1
0
0
0
0
1
1
2
0
0
0
1
0
1
3
0
0
0
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
15
0
1
1
1
1
1
16
1
0
0
0
0
1
Receive Mode Register
This register contains six bits which control receiver
function, and one receive buffer status bit. See Table 11.
The status bit, RX BUF EMPTY (Receive Buffer
Empty), is very important to the software routine which
reads receive packets from the buffer. It tells the host
routine whether there are any packets in the receive buffer
which are complete and ready to read. In a multi-tasking
system, this indicator would be used in conjunction with
an interrupt when RX PKT asserts, which means a packet
has arrived in memory. The interrupt would be used to
start the routine which reads packets from the buffer. As
this routine begins, the interrupt on RX PKT can be
disabled to prevent unneeded interrupts. After the first
packet is read from the buffer, the RX BUF EMPTY bit
would be read to see if any more packets have come in
(packets may, at times, arrive in bursts). If the buffer is not
empty, another packet would be read out, and this
procedure repeated until the buffer is empty. After
emptying the buffer, the host clears RX PKT, then
re-enables interrupts on RX PKT, checks the buffer status
one more time (since a packet can come in at any time),
then exits to do other tasks.
相關(guān)PDF資料
PDF描述
MB86960APF-G NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)
MB86961A UNIVERSAL INTERFACE FOR 10BASET
MB86961APD-G UNIVERSAL INTERFACE FOR 10BASET
MB86961APF-G UNIVERSAL INTERFACE FOR 10BASET
MB86965 EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86960APF-G 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)
MB86961A 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET
MB86961APD-G 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET
MB86961APF-G 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET
MB86965 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*