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參數(shù)資料
| 型號： | MB86942 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Peripheral LSI for SPARClite |
| 中文描述： | 外圍LSI的SPARClite |
| 文件頁數(shù)： | 11/49頁 |
| 文件大?。?/td> | 598K |
| 代理商： | MB86942 |
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11
MB86941/942
4. SDTR SIGNALS (24)
(Continued)
Pin symbol
I/O
Pin no.
Pin name
Description
DSR0#
I
26
Data Set Ready 0
Modem control signal DSR input pin
The status of these pins is indicated at the status
register bit 7.
DSR1#
I
60
Data Set Ready 1
RTS0#
O
28
Request To Send 0
Modem control signal RTS output pin
Set the command register bit 5 to “1” to output an “L”
signal, or to “0” to output an “H” signal.
RTS1#
O
58
Request To Send 1
DTR0#
O
31
Data Terminal Ready 0
These pins can be used as a DATA TERMINAL
READY signal or a RATE SELECT signal of
modem.Set the command register bit 1 to “1” to output
an “L” signal, or to “0” to output an “H” signal.
DTR1#
O
56
Data Terminal Ready 1
CTS0#
I
27
Clear To Send 0
Modem CLEAR TO SEND pin
To enable sending, the command register bit 0 must
be set to “1” and also an “L” level signal must be input
at these pins.
CTS1#
I
59
Clear To Send 1
TRNDT0
O
29
Transmit Data 0
Transmit Data pin
Parallel data written to the data register is converted to
serial data and output from these pins.
In asynchronous mode, a start bit and stop bit are
attached, and a parity bit may be attached if
necessary.
If there is no data to be sent in the SDTR module, in
synchronous mode a synchronizing character is output
and in asynchronous mode the pins go to mark mode.
If a send-prohibited setting (command register bit 0 set
to “0”) is in effect, or if an “H” signal is input at the
CTS# pin, these pins to mark mode. However if a
send-prohibited setting is entered while a sending
operation is in progress, all sending data already
written will be sent before these pins go to mark mode.
In addition, in bisynchronous mode if the first
synchronization character is being sent
(synchronization standby), then these pins will go to
mark mode after sending the second synchronization
character.
TRNDT1
O
57
Transmit Data 1
TEMP0
O
42
Transmit Empty 0
These pins indicate whether sending data is present.
If there is no data to be sent in the SDTR module, the
signal level is “H.”
As soon as one byte of sending data is written, these
pins go to “L” level at the fall of the write signal.
TEMP1
O
46
Transmit Empty 1
TRDY0
O
33
Transmit Ready 0
Transmit Ready output pin
When the CTS# signal is “L” and the command
register is set to enable sending, these pins send an
“H” level signal whenever the sending data buffer is
empty.
TRDY1
O
52
Transmit Ready 1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB86942PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86950BPD-G | 制造商:FUJITSU 功能描述: |
| MB86960 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| MB86960APF-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| MB86961A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
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