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參數(shù)資料
| 型號： | MB86615PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | IEEE 1394 Bus Controller (for DVC) |
| 中文描述： | 2 CHANNEL(S), 98.304M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 44/48頁 |
| 文件大?。?/td> | 633K |
| 代理商： | MB86615PFV |
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44
MB86615
3. Bank 1 Registers
Bank 1 contains the registers required for AV/C (DVC) protocols.
Access to this bank is enabled by writing ‘0001h’ to the bank select register (3Eh).
Address
HEX
A5
A4
A3
A2
A1
Sending time stamp offset
Write operation
Read operation
10
0
1
0
0
0
setting register
Receiving time stamp offset
setting register
Sending CIP header DBS
setting register
←
12
0
1
0
0
1
←
14
0
1
0
1
0
Receiving CIP header
display register (highest)
Receiving CIP header
display register (high)
Receiving CIP header
display register (low)
Receiving CIP header
display register (lowest)
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
16
0
1
0
1
1
(reserved)
18
0
1
1
0
0
Sending CIP header FMT
setting register
1A
0
1
1
0
1
(reserved)
1C
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OMPR (high)
OMPR (low)
OPCR0 (high)
OPCR0 (low)
(reserved)
(reserved)
(reserved)
(reserved)
IMPR (high)
IMPR (low)
IPCR0 (high)
IPCR0 (low)
(reserved)
(reserved)
(reserved)
(reserved)
set-PCR & FP-timeout setting register
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