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參數(shù)資料
| 型號： | MB86615PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | IEEE 1394 Bus Controller (for DVC) |
| 中文描述： | 2 CHANNEL(S), 98.304M bps, SERIAL COMM CONTROLLER, PBGA120 |
| 封裝： | PLASTIC, FBGA-120 |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 633K |
| 代理商： | MB86615PBT |
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MB86615
I
BLOCK DESCRIPTIONS
PHY Layer Control Circuit
This block contains the IEEE 1394 physical layer control circuits.
Both asynchronous transfer and isochronous transfer in a cable environment are supported.
The transfer speed is 100 Mbit/sec.
One analog transceiver/receiver ports are built-in.
This block provides bus status monitoring initialization operation after a bus reset is applied, as well as
arbitration and encoding/decoding functions for data sending and receiving.
LINK Layer Control Circuit
This block controls the generation and transfer of IEEE 1394 standard packets.
32-bit CRC generation and checking is performed for packet headers and data.
A 32-bit cycle timer register is built-in to provide cycle master functions.
Sending/Receiving FIFO
Contains built-in 1-byte FIFO areas, used for isochronous transfer for both sending
and receiving.
Contains independent sending and receiving 128-byte FIFO areas for asynchronous transfer.
Packet Processing
Sending: Performs packetizing of headers, data and CRC. Automatically generates and attaches CRC.
Receiving: Separates 1394 packet headers and data, strips CRC.
Transaction Control Circuit Block
This block controls the 1394 bus protocol based on a variety of instructions.
Dedicated Transaction Circuit Block
This block packetizes data from the isochronous interface for DVC and rebuilds received data for the
isochronous interface in conjunction with the packet processing block.
Register Block
This block contains various device control registers, as well as registers for setting parameters required for
transfer, DVC registers and CSR.
The built-in CSR provides isochronous resource manager functions.
PLL Circuit
This block uses the reference clock signal generated by the crystal oscillator circuit to create internal operating
clock and transfer clock signals.
Reference oscillator frequency: 8.192 MHz.
相關PDF資料 |
PDF描述 |
|---|---|
| MB86615PFV | IEEE 1394 Bus Controller (for DVC) |
| MB86616 | IEEE1394-SCSI Tailgate |
| MB86616PFV-G-BND | IEEE1394-SCSI Tailgate |
| MB86831 | 32-bit Embedded Controller |
| MB86836-108PMT2 | 32-bit Embedded Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB86615PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for DVC) |
| MB86616 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE1394-SCSI Tailgate |
| MB86616PFV-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE1394-SCSI Tailgate |
| MB86619 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Serial Bus Controller for DTV |
| MB86626 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:KeyWave AFE ADSL Analog Front End |
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