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參數(shù)資料
| 型號(hào)： | MB86615 |
| 廠商： | Fujitsu Limited |
| 英文描述： | IEEE 1394 Bus Controller (for DVC) |
| 中文描述： | 1394總線控制器（于DVC） |
| 文件頁數(shù)： | 43/48頁 |
| 文件大?。?/td> | 633K |
| 代理商： | MB86615 |
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MB86615
2. Bank 0 Registers
Bank 0 contains the registers required for 1394 settings and transfers.
Access to this bank is enabled by writing ‘0000h’ to the bank select register (3Eh).
Address
Write operation
HEX
A5
A4
A3
A2
A1
Sending ISO PKT header
setting register (high)
Sending ISO PKT header
setting register (low)
Sending ASYNC des ID
Read operation
10
0
1
0
0
0
Receiving ISO PKT header
display register (high)
Receiving ISO PKT header
display register (low)
Receiving ASYNC des ID
setting register
Receiving ASYNC PKT param
display register
Receiving ASYNC data length
display register
Receiving ASYNC ex tcode
display register
Receiving ASYNC source ID
display register
Receiving ASYNC resp param
display register
Receiving ASYNC des offset
display register (high)
Receiving ASYNC des offset
display register (middle)
Receiving ASYNC des offset
display register (low)
←
PHY ID display register
NODE config display register
←
PORT config display register
root ID display register
ISO resource manager ID
display register
12
0
1
0
0
1
14
0
1
0
1
0
setting register
Sending ASYNC PKT param
setting register
Sending ASYNC data length
setting register
Sending ASYNC ex tcode
setting register
Sending ASYNC source ID
setting register
Sending ASYNC resp param
setting register
Sending ASYNC des offset
setting register (high)
Sending ASYNC des offset
setting register (middle)
Sending ASYNC des offset
setting register (low)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
state clear setting register
16
0
1
0
1
1
18
0
1
1
0
0
1A
0
1
1
0
1
1C
0
1
1
1
0
1E
0
1
1
1
1
20
1
0
0
0
0
22
1
0
0
0
1
24
1
0
0
1
0
26
28
2A
2C
2E
30
1
1
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
32
1
1
0
0
1
Self ID PKT param setting register
34
1
1
0
1
0
Receiving ISO-channel
setting register (0, 1)
Receiving ISO-channel
setting register (2, 3)
←
36
1
1
0
1
1
←
38
1
1
1
0
0
(reserved)
cycle timer monitor
display register (high)
cycle timer monitor
display register (low)
←
3A
1
1
1
0
1
(reserved)
3C
1
1
1
1
0
(reserved)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86615PBT | IEEE 1394 Bus Controller (for DVC) |
| MB86615PFV | IEEE 1394 Bus Controller (for DVC) |
| MB86616 | IEEE1394-SCSI Tailgate |
| MB86616PFV-G-BND | IEEE1394-SCSI Tailgate |
| MB86831 | 32-bit Embedded Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86615PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for DVC) |
| MB86615PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for DVC) |
| MB86616 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE1394-SCSI Tailgate |
| MB86616PFV-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE1394-SCSI Tailgate |
| MB86619 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Serial Bus Controller for DTV |
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