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參數(shù)資料
| 型號： | MB86613 |
| 廠商： | Fujitsu Limited |
| 英文描述： | RES 3.0 OHM 1/16W 5% 0402 SMD |
| 中文描述： | 1394控制器的開放式人機(jī)交互 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大小： | 473K |
| 代理商： | MB86613 |
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MB86613
14
I
BLOCK DESCRIPTION
Parallel ROM I/F
This block is the parallel port ROM interface to which EPROM (BIOS ROM) with a data width of 8 bits and that
EEPROM (PCI configuration ROM) are connected which contains PCI subsystem ID and subsystem vendor ID
information. For details, see “
I
COMPONENT CONNECTION DIAGRAM 3. Memory Interface”
CPC (context program controller)
This block analyzes context programs stored in host memory to store the packet to be sent out from host memory
to the FIFO buffer or to store the received packet from the FIFO buffer to host memory (AR-CPC, IR-CPC).
Upon reception of a physical request packet, this block analyzes the packet automatically for servicing the request
(phys-req unit).
CPC work memory
This block is work memory which stores context programs prepared in host memory or packet header information
upon reception of a physical request packet.
OHCI register
This block holds 2048 bytes of registers defined in the Open HCI Standard.
FIFO
This block is a 6-KB FIFO buffer. This FIFO consists of a transmit-packet storage area (AT-FIFO and IT-FIFO)
and a receive-packet storage area (AR-FIFO and IR-FIFO), each of which is freely addressable.
LINK-Rx
This block stores the LINK-received, 1394-formatted packet in the FIFO buffer, with trailer data defined in the
Open HCI Standard added.
LINK-Tx
This block converts the packet stored in the FIFO buffer into the 1394 format and sends it to the LINK.
PCI I/F
This block provides PCI bus protocol control.
PCI-DMAC
This block issues a transfer request with the MB86613 serving as the bus master.
PCI-slave
This block responds to the register access from the bus master.
LINK core
This block generates data CRC and header CRC, transmits the selfID packet, and controls packet transmission
and reception.
PHY
This block provides 1394 bus protocol control.
Bus manager
This block manages the cycle timer, generates a variety of interrupts, and holds the bus management CSR.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86613PBT | IEEE 1394 Open HCI Controller |
| MB86613PFV | IEEE 1394 Open HCI Controller |
| MB86615 | IEEE 1394 Bus Controller (for DVC) |
| MB86615PBT | IEEE 1394 Bus Controller (for DVC) |
| MB86615PFV | IEEE 1394 Bus Controller (for DVC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86613PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613S | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE1394 Open HCI Controller |
| MB86614APFV-G-BND | 制造商:FUJITSU Component Ltd 功能描述: 制造商:FUJITSU 功能描述: |
| MB86615 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for DVC) |
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