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2
MB86605
I
FEATURES
SCSI Protocol Controller Block:
Operable as initiator and target
WIDE and FAST data transfer
– Synchronous transfer (max. 20 Mbytes/s: Up to 32 offset values can be set.)
– Asynchronous transfer (max. 10 Mbytes/s)
64-byte FIFO register for data phase
Two types (send-only and receive-only) of 32-byte data buffers for message, command, and status phases
(MCS Buffers)
On-chip totem pole type SCSI single-ended driver/receiver
Supports external SCSI differential driver/receiver
On-chip memory to store transfer parameters (up to 15 connected devices) for each ID
On-chip 16-bit transfer block counter and 24-bit transfer byte counter
– Maximum Transfer Byte
: 1 Tbyte at fixed length data transfer
: 6 Mbyte at variable length data transfer
Supports various control commands:
– Sequential Commands
: can perform phase-to-phase sequential operations (functions only when
issuing from a system side.)
– Discrete Commands
: can perform any desired sequence to program in the user program memory
– Data Transfer Commands : can program the transfer data length at the user program operation.
On-chip direct control register for SCAM (SCSI Configured AutoMatically)
Supports Multi Selection/Reselection Responses
– Selection and Reselection responses can be done to plural IDs.
On-chip 2 Kbyte User Program Memory
– Two Modes: 2 Kbyte
×
1 bank and 1 Kbyte
×
2 banks
(While 1 Kbyte
×
2 banks are selected, host system can access another bank even if the user
program is executing.)
– Access to User program
: Burst transfer via I/O access port
: Direct access to 2 Kbyte user program memory (only for PCI bus I/F mode)
User Selectable Interrupt Report
– Unnecessary interrupt reports can be disabled depending on user's applications to reduce a system ISR
overhead.
Two automatic receive modes
– Initiator : can automatically receive information for new phase to which target switched
– Target
: can automatically receive attention condition generated by initiator
Automatic selection/reselection
– For command issues
: automatically performs to receive MSG/CMD to the selection/reselection
request from partner device
– For user program operation: pauses the program currently executed and automatically jumps to the
specified selection/reselection routine in response to the selection/reselection
request from partner device.
Operation Clock
– System Clock: Max. 40 MHz
– Internal Processor Operating Clock: Max. 20 MHz
(Continued)