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參數(shù)資料
| 型號(hào)： | MB86060PFV |
| 廠商： | Fujitsu Limited |
| 元件分類： | DAC |
| 英文描述： | 16-Bit Interpolating Digital to Analog Converter |
| 中文描述： | 16位插數(shù)模轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | MB86060PFV |
June 2000
Version 1.2
FME/MS/SFDAC1/FL_1/4270
MB86060
16-Bit Interpolating Digital to Analog Converter
Page 2 of 6
Copyright 2000 Fujitsu Microelectronics Europe GmbH
Functional Description
The MB86060 integrates a 12-bit 400MSa/s DAC with selectable front end processing to provide input
interpolation filtering, dither and noise shaping. Versatile interfacing via the 16-bit parallel CMOS data input
allows different system requirements to be accommodated, with either offset binary or 2’s complement data
formats selected by an input format control.
The device is manufactured in a 0.35μm advanced CMOS process with Triple Well extension giving
improved isolation between analog blocks and digital-analog.
MB86060 Functional Block Diagram
Converter Architecture
The MB86060 Interpolating DAC incorporates a number of novel design aspects that are subject to patent
applications. Key to its operation are the current sources where segmented, common centroid, interleaved
techniques for the most significant bits, as well as load matching ensure good linearity and low distortion
to at least the 12-bit level. In the switch elements tracking capacitance is minimised to improve settling,
while controlled rise and fall times improve SFDR performance. Finally the digital decoding uses a 3-
dimensional addressing approach to minimise propagation delays from latch to element.
FML Mixed Signal
DAC
g
Dither
Generator
Clock
Multiplier
12
16
Data In
CLK in (diff.)
DAC
Output
Dither
Reset
Noise
Shaper
x2
Bandgap
Reference
Filter control
NS Enable
x2
HP Filter
Mult mode
Delay line ctrl
3
2
3
Data CLK out
(diff.)
Data Format
Lock
[x2 slow]
[x2 fast]
16
2
Crystal
Shuffle
Control
2
Clk Select
Over
Clock Divider
2
Programmable
Dithermay be
excluded from
final MP
devices
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