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參數(shù)資料
| 型號： | MB8504E036AA-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4 M×36 BITS Hyper Page Mode DRAM Module(CMOS 4 M×36 位超級頁面存取模式動態(tài)RAM模塊) |
| 中文描述： | 4米× 36位超頁模式內(nèi)存的CMOS（4米× 36位超級頁面存取模式動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 240K |
| 代理商： | MB8504E036AA-70 |
DS05-11239-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
4 M
HYPER PAGE MODE DRAM MODULE
×
36 BIT
MB8504E036AA-60/-70
4M
×
36 BIT Hyper Page Mode DRAM Module, 5 V, 1-Bank
I
DESCRIPTION
The Fujitsu MB8504E036AA is a fully decoded, CMOS Dynamic Random Access Memory (DRAM) module
consisting of eight MB8117405A and four MB814105C devices. The MB8504E036AA is optimized for those
applications requiring high speed, high performance and large memory storage. The operation and electrical
characteristics of the MB8504E036AA are the same as the MB8117405A which features hyper page mode
operation providing extended valid time for data output and higher speed random access of upto 2,048-bit of data
within the same row than the fast page mode. For ease of memory expansion, the MB8504E036AA is offered
in a 72-pad Single In-line Memory Module package (SIMM).
I
PRODUCT LINE & FEATURES
Parameter
MB8504E036AA-60
MB8504E036AA-70
RAS Access Time
60 ns max.
70 ns max.
Random Cycle Time
104 ns min.
124 ns min.
Address Access Time
30 ns max.
35 ns max.
CAS Access Time
15 ns max.
20 ns max.
Hyper Page Mode Cycle Time
25 ns min.
30 ns min.
Power Dissipation
Operating Mode
5962 mW max.
5148 mW max.
Standby Mode
66 mW (CMOS) / 132 mW (TTL)
Organization : 4,194,304 words
×
36 bits
Memory : MB8117405A, 8 pcs
MB814105C, 4 pcs
5.0 V
±
10% Supply Voltage
2,048 Refresh Cycles / 32.8 ms
Hyper page mode operation (EDO)
Package and Ordering Information:
72-pin SIMM, order as
MB8504E036AA-xxSG
(SG = Gold Pad)
MB8504E036AA-xxSS
(SS = Solder Pad)
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