參數(shù)資料
型號(hào): MB8501S064AD-84
廠商: Fujitsu Limited
英文描述: CMOS 1M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 1M×64位同步動(dòng)態(tài)RAM)
中文描述: 的CMOS 100萬(wàn)× 64位同步動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器(SDRAM)的CMOS(100萬(wàn)× 64位同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 1/19頁(yè)
文件大?。?/td> 326K
代理商: MB8501S064AD-84
DS05-11104-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
Un-buffered
1 M
SYNCHRONOUS DYNAMIC RAMSO-DIMM
×
64 BIT
MB8501S064AD-100/-84/-67
144-pin, 1 Clock, 1-bank, based on 1 M
×
16 BIT SDRAMs with SPD
I
DESCRIPTION
The Fujitsu MB8501S064AD is a fully decoded, CMOS Synchronous Dynamic Random Access Memory
(SDRAM) Module consisting of four MB811171622A devices which organized as two banks of 1 M
a 2K-bit serial EEPROM on a 144-pin glass-epoxy substrate.
The MB8501S064AD features a fully synchronous operation referenced to a positive edge clock whereby all
operations are synchronized at a clock input which enables high performance and simple user interface
coexistence.
The MB8501S064AD is optimized for those applications requiring high speed, high performance and large
memory storage, and high density memory organizations.
This module is ideally suited for workstations, PCs, laser printers, and other applications where a simple interface
is needed.
×
16 bits and
I
PRODUCT LINE & FEATURES
Parameter
MB8501S064AD-100
100 MHz max.
10 ns max. (CL = 3)
15 ns max. (CL = 2)
54 ns max.
24 ns max.
8.5 ns max. (CL = 3)
9 ns max. (CL = 2)
1944 mW max.
MB8501S064AD-84
84 MHz max.
12 ns max. (CL = 3)
17 ns max. (CL = 2)
56 ns max.
26 ns max.
8.5 ns max. (CL = 3)
9 ns max. (CL = 2)
1800 mW max.
28.8 mW max.
MB8501S064AD-67
67 MHz max.
15 ns max. (CL = 3)
20 ns max. (CL = 2)
60 ns max.
30 ns max.
9 ns max. (CL = 3)
10 ns max. (CL = 2)
1620 mW max.
Clock Frequency
Burst Mode Cycle Time
RAS Access Time
CAS Access Time
Output Valid from Clock
Power
Dissipation
Burst Mode
Power Down Mode
Un-buffered 144-pin DIMM Socket Type
(Lead pitch: 0.8 mm)
Conformed to JEDEC Standard (1 CLK)
Organization: 1,048,576 words
×
64 bits
Memory : MB81117622A (1 M
×
16, 2-bank)
×
4 pcs.
3.3 V
±
0.3 V Supply Voltage
All input/output LVTTL compatible
2048 Refresh Cycle every 32.8 ms
Auto and Self Refresh
CKE Power Down Mode
DQM Byte Masking (Read/Write)
Serial Presence Detect (SPD) with Serial EEPROM
Module size:
1.0” (height)
×
2.66” (length)
×
0.15” (thick)
相關(guān)PDF資料
PDF描述
MB8501S064AE-100 CMOS 1M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 1M×64位 同步動(dòng)態(tài)RAM)
MB8501S064AE-67 CMOS 1M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 1M×64位 同步動(dòng)態(tài)RAM)
MB8501S064AE-84 CMOS 1M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 1M×64位 同步動(dòng)態(tài)RAM)
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