![](http://datasheet.mmic.net.cn/330000/MB84VA2100_datasheet_16435960/MB84VA2100_25.png)
25
MB84VA2100
-10
/MB84VA2101
-10
Write Cycle (Note 4) (CE2s Control) (SRAM)
t
WC
t
AS
t
WP
t
WR
t
CW
t
ODW
t
COE
t
DS
t
DH
VALID DATA IN
ADDRESSES
WE
CE1s
D
OUT
D
IN
CE2s
Notes:
2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the
output will remain at high impedance.
3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the
output will remain at high impedance.
4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
Note 5
Note 5
t
CW