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| 型號： | MB81117422A-100 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動態(tài)RAM) |
| 中文描述： | 的CMOS 2 × 200萬× 4位同步動態(tài)RAM（2 × 200萬的CMOS × 4位同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 273K |
| 代理商： | MB81117422A-100 |
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28
MB81117422A-125/-100/-84/-67
LATENCY-FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Notes:
*1.
I
CC
depends on the output termination or load conditions, clock cycle rate, and signal clocking rate;
The specified values are obtained with the output open and no termination register.
An initial pause (DESL or NOP) of 200
μ
s is required after power-up followed by a minimum of eight
Auto-refresh cycles.
AC characteristics assume t
T
= 1 ns and 30 pF of capacitive load.
1.4 V is the reference level for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max).
Assumes t
RCD
and t
CAC
are satisfied.
t
AC
also specifies the access time at burst mode except for first access.
Specified where output buffer is no longer driven.
Actual clock count of t
RC
(l
RC
) will be sum of clock count of t
RAS
(l
RAS
) and t
RP
(l
RP
).
t
RAC
is a reference value. Maximum value is obtained from the sum of t
RCD
(min) and t
CAC
(max).
Assumes t
RAC
and t
AC
are satisfied.
Operation within the t
RCD
(min) ensures that t
RAC
can be met; if t
RCD
is greater than the specified t
RCD
(min), access time is determined by t
CAC
or t
AC
.
All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula: clock count equals base value
divided by clock period (round off to a whole number).
The t
CAC
is programmed by the mode register.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
*11.
*12.
*13.
Parameter
Notes
Symbol
MB81117422A
-125
MB81117422A
-100
MB81117422A
-84
MB81117422A
-67
Unit
CKE to Clock Disable
l
CKE
1
1
1
1
cycle
DQM to Output in High-Z
l
DQZ
2
2
2
2
cycle
DQM to Input Data Delay
l
DQD
0
0
0
0
cycle
Last Output to Write
Command Delay
l
OWD
2
2
2
2
cycle
Write Command to Input
Data Delay
l
DWD
0
0
0
0
cycle
Precharge to Output in
High-Z Delay
CL = 2
l
ROH
2
2
2
2
cycle
CL = 3
3
3
3
3
cycle
Burst Stop Command to
Output in High-Z Delay
CL = 2
l
BSH
2
2
2
2
cycle
CL = 3
3
3
3
3
cycle
Mode Register Access to
Banks Active
l
MRD
2
2
2
2
cycle
CAS to CAS Delay (min)
l
CCD
1
1
1
1
cycle
CAS Bank Delay (min)
l
CBD
1
1
1
1
cycle
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