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| 型號(hào)： | MB811171622A-67 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM) |
| 中文描述： | 的CMOS為512k × 2 × 16位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（2 ×的CMOS為512k × 16位同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 601K |
| 代理商： | MB811171622A-67 |
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MB811171622A-125/-100/-84/-67
I
FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode,
and mode register.
The
synchronized operation
is the fundamental difference. An SDRAM uses a clock input for the synchronization,
where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each
operation of DRAM is determined by their timing phase difference while each operation of SDRAM is determined
by commands and all operations are referenced to a positive clock edge. Fig 3 show the basic timing diagram
differences between SDRAMs and DRAMs.
The
burst mode
is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column address
counter.
The
mode register
is to justify the SDRAM operation and function into desired system conditions. MODE
REGISTER TABLE shows how SDRAM can be configured for system requirement by mode register programming.
CLOCK (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and
internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the
CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the
next clock will be internally masked. During idle state (all banks have been precharged), the power Down mode
(standby) is entered with CKE = Low and this will make extremely low standby current.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals are
negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS can be
tied to ground level.
COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address
strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge
of the CLK determines SDRAM operation. Refer to FUNCTION TRUTH TABLE in page 5.
ADDRESS INPUT (A
0
to A
10
)
Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of nineteen
address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order to
reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row addresses are initially
latched and the remainder of eight Column addresses are then latched by a Column address strobe command of
either a Read command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (A
11
)
This SDRAM has two banks and each bank is organized as 512K words by 16-bit.
Bank selection by A
11
occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT
or WRITA), and precharge command (PRE).
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