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參數(shù)資料
| 型號(hào)： | MB40950 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 3-Channel 10-Bit D/A Converter(三通道10位 D/A轉(zhuǎn)換器) |
| 中文描述： | 3通道10位D / A轉(zhuǎn)換器（三通道10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 206K |
| 代理商： | MB40950 |
9
MB40950
I
CALCULATION OF DAC OUTPUT VOLTAGE AT IDEAL CONVERSION
I
NOTES ON USE
1. Power Supply Patterns of the PCB
The power supply wire patterns (V
CC
and GND patterns) of the PCB should be designed as wide as possible
in order to reduce parasitic impedance.
2. Switching Noise
In order to reduce switching noise as much as possible, noise limit capacitor must be connected between V
CCD
and D. GND pins and V
CCA
and A. GND pins.
In this case, the capacitor should be connected to the GND pins side as near as possible.
R
OUT
(G
OUT
, B
OUT
) = V
CCA
–1023 – N
CCA
– V
RIN
)
1024
[ N : Digital Input Code (0 to 1023) ]
V
OFS
= V
CCA
V
OZS
= V
CCA
– 1023
CCA
– V
RIN
)
1024
5V
V
CCD
0.01
μ
F
47
μ
F
47
μ
F
0.01
μ
F
2.2
μ
H
2.2
μ
H
V
CCA
R
1
to
10
G
1
to
10
B
1
to
10
D. GND
A. GND
R
OUT
G
OUT
B
OUT
V
ROUT2
V
RIN
V
ROUT1
COMP
0.1
μ
F
Data Input
CLK Input
Connect to V
ROUT1
, V
ROUT2
, or
external reference voltage source.
CLKR
CLKG
CLKB
I
TYPICAL CONNECTION EXAMPLE
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