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參數(shù)資料
| 型號： | MB3893APFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 電源管理 |
| 英文描述： | Bridge Rectifier; Current Rating:260A; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
| 中文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 35/44頁 |
| 文件大?。?/td> | 496K |
| 代理商： | MB3893APFV |
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MB3893A
35
b) 1.5
<
t
<
0 s
The MB3893A power supply drop detection intervals are set to t
DET1
(10 s (Typ.)) and t
DET2
(1.5 s (Typ.)) so that,
as shown in Figure 9(b), when VCC goes from “H” level to “L” level, the OUT1 (pin 29), OUT2 (pin 30), and OUT4
(pin 22) terminals go to “L” level, and the XRST terminal (pin 35) also goes to “L” level. At this time, the VBDET1
terminal (pin 34) and VBDET2 terminal (pin 33) also go to “L” level. When VCC drops for a fixed interval (1.5 s
< t < 10 s), and then returns to “H” level, the OUT1, OUT2, and OUT4 terminals after a delay interval (tR2) output
their regulated voltages, and the XRST terminal after a delay interval (t
POR
) goes to “H” level. During the interval
between the VCC drop and XRST terminal return to “H” level the VBDET1 terminal and VBDET2 terminal are
in undefined state. Also once the XRST terminal returns to “H” level the VBDET1 terminal is at “H” level and the
VBDET2 terminal is also at “H” level. At this time, if the DRST terminal (pin 5) goes to “H” level, the VBDET1
and VBDET2 terminals remain at “H” level. Note that the DRST terminal must be at “H” level for at least an
interval of 10
μ
s.
Figure 9. Power Supply Drop Detector 2 (Initial power supply detector/Power supply drop detector)
b) 1.5
<
t
<
10 s
V
CC
VDET
(IC internal)
OUT1,
OUT2,
OUT4
XRST
VBDET2
VBDET1
DRST
t
DROP
DON'T CARE
t
R2
t
POR
10
μ
s (Min.)
DON'T CARE
DON'T CARE
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