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參數(shù)資料
| 型號： | MB15F76UV |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | ASSP Dual Serial Input PLL Frequency Synthesizer(Small Package) |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 6000 MHz, PQCC18 |
| 封裝： | PLASTIC, BCC-18 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 151K |
| 代理商： | MB15F76UV |
3
MB15F76UV
Aug. 2003
Edition 0.2
PIN DESCRIPTIONS
Pin No.
Pin
name
I/O
Descriptions
1
GND
-
Ground for OSC input buffer and the shift registor circuit.
2
fin
IF
I
Prescaler input pin for the IF-PLL section.
Connection to an external VCO should be AC coupling.
3
Xfin
IF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
4
GND
IF
-
Ground for the IF-PLL section.
5
Vcc
IF
-
Power supply voltage input pin for the IF-PLL section(except for the
charge pump circuit), the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
6
Do
IF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
7
PS
IF
I
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PS
IF
= ”H” ; Normal mode PS
IF
= ”L” ; Power saving mode
8
LD/fout
O
Lock detect signal output(LD)/ phase comparator monitoring outut
(fout). The output signal is selected by a LDS bit in a serial data.
LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal
9
PS
RF
I
Power saving mode control for the RF-PLL section. This pin must be
set at ”L” Power-ON. (Open is prohibited.)
PS
RF
= ”H” ; Normal mode PS
RF
= ”L” ; Power saving mode
10
Do
RF
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
11
Vcc
RF
-
Power supply voltage input pin for the RF-PLL section(except for the
charge pump circuit).
12
GND
RF
-
Ground for the RF-PLL section.
13
Xfin
RF
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
14
fin
RF
I
Prescaler input pin for the RF-PLL.
Connction to an external VCO should be AC coupling.
15
LE
I
Load enable signal input (with the schmitt trigger circuit.)
When LE is set "H", data in the shift register is transferred to the corre-
sponding latch according to the control bit in a serial data.
16
Data
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
17
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the
clock.
18
OSC
IN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
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| MB15F78SP | Dual Serial Input PLL Frequency Synthesizer |
| MB15F78SPPFT | Dual Serial Input PLL Frequency Synthesizer |
| MB15F78SPPV | Dual Serial Input PLL Frequency Synthesizer |
| MB15F78UL | Dual Serial Input PLL Frequency Synthesizer |
| MB15F78ULPFT | Dual Serial Input PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F78SP | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F78SPPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F78SPPV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F78UL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F78ULPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
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