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參數(shù)資料
| 型號(hào)： | MB15F73SPPV |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PBCC20 |
| 封裝： | PLASTIC, BCC-20 |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 155K |
| 代理商： | MB15F73SPPV |
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3
MB15F73UL
Dec. 2000
Edition 2.0
n
PIN DESCRIPTIONS
Pin No.
Pin
name
I/O
Descriptions
TSSOP
BCC
1
19
OSC
IN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
2
20
GND
-
Ground for OSC input buffer and the shift registor circuit.
3
1
fin
IF
I
Prescaler input pin for the IF-PLL section.
Connection to an external VCO should be AC coupling.
4
2
Xfin
IF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
5
3
GND
IF
-
Ground for the IF-PLL section.
6
4
Vcc
IF
-
Power supply voltage input pin for the IF-PLL section(except for the
charge pump circuit), the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
7
5
PS
IF
I
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PS
IF
= ”H” ; Normal mode PS
IF
= ”L” ; Power saving mode
8
6
Vp
IF
-
Power supply voltage input pin for the IF-PLL charge pump.
9
7
Do
IF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
10
8
LD/fout
O
Lock detect signal output(LD)/ phase comparator monitoring outut
(fout). The output signal is selected by a LDS bit in a serial data.
LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal
11
9
Do
RF
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
12
10
Vp
RF
-
Power supply voltage input pin for the RF-PLL charge pump.
13
11
PS
RF
I
Power saving mode control for the RF-PLL section. This pin must be
set at ”L” Power-ON. (Open is prohibited.)
PS
RF
= ”H” ; Normal mode PS
RF
= ”L” ; Power saving mode
14
12
Vcc
RF
-
Power supply voltage input pin for the RF-PLL section(except for the
charge pump circuit).
15
13
GND
RF
-
Ground for the RF-PLL section.
16
14
Xfin
RF
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
17
15
fin
RF
I
Prescaler input pin for the RF-PLL.
Connction to an external VCO should be AC coupling.
18
16
LE
I
Load enable signal input (with the schmitt trigger circuit.)
When LE is set "H", data in the shift register is transferred to the corre-
sponding latch according to the control bit in a serial data.
19
17
Data
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
20
18
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the
clock.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F73UL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:ASSP Dual Serial Input PLL Frequency Synthesizer |
| MB15F73UL_01 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F73ULPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F73ULPFT-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB15F73ULPFT-G-BND-EFE1 | 功能描述:IC SYNTHESIZR PLL DL INP 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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