- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377878 > MB15F72SPPV (FUJITSU LTD) Dual Serial Input PLL Frequency Synthesizer PDF資料下載
參數(shù)資料
| 型號： | MB15F72SPPV |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PBCC20 |
| 封裝： | PLASTIC, BCC-20 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 279K |
| 代理商： | MB15F72SPPV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
MB15F72UL
8
I
FUNCTIONAL DESCRIPTION
1.
Pulse swallow function :
f
VCO
=
[ (P
×
N)
+
A]
×
f
OSC
÷
R
f
VCO
: Output frequency of external voltage controlled oscillator (VCO)
P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0
≤
A
≤
127, A
<
N)
f
OSC
: Reference oscillation frequency (OSC
IN
input frequency)
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2.
Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/
RF-PLL sections, and programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On a rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
(1)
Shift Register Configuration
The programmable
reference counter
for the IF-PLL
The programmable
reference counter
for the RF-PLL
The programmable
counter and the swallow
counter for the IF-PLL
The programmable
counter and the swallow
counter for the RF-PLL
CN1
0
1
0
1
CN2
0
0
1
1
(LSB)
(MSB)
Data Flow
Programmable Reference Counter
Note : Data input with MSB first.
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
16
17
18
19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS
X
X
X
X
CS
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, T2
: LD/fout output setting bit.
CN1, CN2 : Control bit
X
: Dummy bits (Set “0” or “1”)
: Charge pump curre
n
t select bit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB15F73ULPFT | Dual Serial Input PLL Frequency Synthesizer |
| MB15F73ULPVA | Dual Serial Input PLL Frequency Synthesizer |
| MB15F73UL | ASSP Dual Serial Input PLL Frequency Synthesizer |
| MB15F73SPPFT | Dual Serial Input PLL Frequency Synthesizer |
| MB15F73SPPV | Dual Serial Input PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F72UL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72ULPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72ULPFT-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB15F72ULPFT-G-BND-EFE1 | 功能描述:IC SYNTHESIZR PLL DL INP 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| MB15F72ULPVA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。