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參數(shù)資料
| 型號： | MB15F72SP |
| 廠商： | Fujitsu Limited |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | 雙串行輸入鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 279K |
| 代理商： | MB15F72SP |
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MB15F72UL
3
I
PIN DESCRIPTION
Pin no.
TSSOP BCC
Pin name I/O
Descriptions
1
19
OSC
IN
I
The programmable reference divider input. TCXO should be connected with an
AC coupling capacitor.
Ground for OSC input buffer and the shift register circuit.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
Ground for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section (except for the charge
pump circuit) , the OSC input buffer and the shift register circuit.
Power saving mode control for the IF-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited.)
PS
IF
=
“H” ; Normal mode / PS
IF
=
“L” ; Power saving mode
Power supply voltage input pin for the IF-PLL charge pump.
Charge pump output pin for the IF-PLL section.
Lock detect signal output (LD) /phase comparator monitoring
output (fout) pins.The output signal is selected by LDS bit in the serial data.
LDS bit
=
“H” ; outputs fout signal / LDS bit
=
“L” ; outputs LD signal
Charge pump output pin for the RF-PLL section.
Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control pin for the RF-PLL section. This pin must be set at
“L” when the power supply is started up. (Open is prohibited.)
PS
RF
=
“H” ; Normal mode / PS
RF
=
“L” ; Power saving mode
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit)
Ground for the RF-PLL section
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in
the serial data.
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
2
20
GND
3
1
fin
IF
I
4
2
Xfin
IF
I
5
3
GND
IF
6
4
V
CCIF
7
5
PS
IF
I
8
9
6
7
Vp
IF
D
OIF
O
10
8
LD/fout
O
11
12
9
10
D
ORF
Vp
RF
O
13
11
PS
RF
I
14
12
V
CCRF
15
13
GND
RF
16
14
Xfin
RF
I
17
15
fin
RF
I
18
16
LE
I
19
17
Data
I
20
18
Clock
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB15F72SPPFT | Dual Serial Input PLL Frequency Synthesizer |
| MB15F72SPPV | Dual Serial Input PLL Frequency Synthesizer |
| MB15F73ULPFT | Dual Serial Input PLL Frequency Synthesizer |
| MB15F73ULPVA | Dual Serial Input PLL Frequency Synthesizer |
| MB15F73UL | ASSP Dual Serial Input PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F72SPPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72SPPV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72UL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72ULPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72ULPFT-G-BNDE1 | 制造商:FUJITSU 功能描述: |
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