參數資料
型號： MB15F07SL
廠商： Fujitsu Limited
英文描述： Dual Serial Input PLL Frequency Synthesizer
中文描述： 雙串行輸入鎖相環(huán)頻率合成器
文件頁數： 3/27頁
文件大?。?/td> 244K
代理商： MB15F07SL
3
MB15F07SL
I
PIN DESCRIPTIONS
Pin no.
Pin
name
I/O
Descriptions
SSOP-16 BCC-16
1
16
GND
2
–
Ground for PLL 2 section.
2
1
OSC
IN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
3
2
GND
1
–
Ground for the PLL 1 section.
4
3
fin
1
I
Prescaler input pin for the PLL 1.
Connection to an external VCO should be via AC coupling.
5
4
V
CC1
–
Power supply voltage input pin for the PLL 1 section.
6
5
LD/fout
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
7
6
PS
1
I
Power saving mode control for the PLL 1 section. This pin must be set
at “L” during Power-ON. (Open is prohibited.)
PS
1
= “H” ; Normal mode
PS
1
= “L” ; Power saving mode
8
7
Do
1
O
Charge pump output for the PLL 1 section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
9
8
Do
2
O
Charge pump output for the PLL 2 section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
10
9
PS
2
I
Power saving mode control for the PLL 2 section. This pin must be set
at “L” during Power-ON. (Open is prohibited.)
PS
2
= “H” ; Normal mode
PS
2
= “L” ; Power saving mode
11
10
Xfin
2
I
Prescaler complementary input for the PLL 2 section.
This pin should be grounded via a capacitor.
12
11
V
CC2
–
Power supply voltage input pin for the PLL 2 section, the shift register and
the oscillator input buffer. When power is OFF, latched data of PLL 2 is lost.
13
12
fin
2
I
Prescaler input pin for the PLL 2.
Connection to an external VCO should be via AC coupling.
14
13
LE
I
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
15
14
Data
I
Serial data input (with a schmitt trigger input buffer.)
Data is transferred to the corresponding latch (PLL 1-ref counter, PLL 1-
prog. counter, PLL 2-ref. counter, PLL 2-prog. counter) according to the
control bit in the serial data.
16
15
Clock
I
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
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相關代理商/技術參數
參數描述
MB15F07SLPFV1 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer
MB15F07SLPFV1-BND-6E1 功能描述:IC SYNTHSZR PLL 1.1GHZ DL 16SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
MB15F07SLPFV1-BND-EF-6E1 功能描述:IC SYNTHSZR PLL 1.1GHZ DL 16SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
MB15F07SLPFV1-BND-ER-6E1 制造商:FUJITSU 功能描述:
MB15F07SLPFV1-G-BND-6E1 制造商:FUJITSU 功能描述:
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