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參數(shù)資料
| 型號(hào)： | MB15F05LPFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1800 MHz, PDSO16 |
| 封裝： | PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 113K |
| 代理商： | MB15F05LPFV |
3
MB15F05L
I
PIN DESCRIPTION
Pin No.
Pin name I/O
Descriptions
SSOP16
BCC16
1
16
GND
RF
–
Ground for RF–PLL section.
2
1
OSCin
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
3
2
GND
IF
–
Ground for the IF-PLL section.
4
3
fin
IF
I
Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.
5
4
Vcc
IF
–
Power supply voltage input pin for the IF-PLL section.
6
5
LD/fout
O
Lock detect signal output (LD) / phase comparator monitoring output
(fout)
The output signal is selected by a LDS bit in a serial data.
LDS bit = ”H” ; outputs fout signal
LDS bit = ”L” ; outputs LD signal
7
6
PS
IF
I
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PS
IF
= ”H” ; Normal mode
PS
IF
= ”L” ; Power saving mode
8
7
Do
IF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
9
8
Do
RF
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
10
9
PS
RF
I
Power saving mode control for the RF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PS
RF
= ”H” ; Normal mode
PS
RF
= ”L” ; Power saving mode
11
10
Xfin
RF
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
12
11
Vcc
RF
–
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer. When power is OFF, latched data of RF-
PLL is cancelled.
13
12
fin
RF
I
Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.
14
13
LE
I
Load enable signal input (with the schmitt trigger circuit.)
When LE is ”H”, data in the shift register is transferred to the
corresponding
latch according to the control bit in a serial data.
15
14
Data
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
16
15
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the
clock.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F05LPV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F07SL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F07SLPFV1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F07SLPFV1-BND-6E1 | 功能描述:IC SYNTHSZR PLL 1.1GHZ DL 16SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| MB15F07SLPFV1-BND-EF-6E1 | 功能描述:IC SYNTHSZR PLL 1.1GHZ DL 16SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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