參數(shù)資料
型號: MB15F04PFV
廠商: FUJITSU LTD
元件分類: XO, clock
英文描述: Dual Serial Input PLL Frequency Synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20
封裝: PLASTIC, SSOP-20
文件頁數(shù): 11/23頁
文件大?。?/td> 256K
代理商: MB15F04PFV
11
MB15F04
I
PHASE DETECTOR OUTPUT WAVEFORM
Note:
Phase error detection range =
2
π
to +2
π
Pulses on Do
TX/RX
signals are output to prevent dead zone.
LD output becomes low when phase error is t
WU
or more.
LD output becomes high when phase error is t
WL
or less and continues to be so for three cycles or more.
t
WU
and t
WL
depend on OSCin input frequency as follows.
t
WU
> 8/fosc: i.e. t
WU
> 625ns when foscin = 12.8 MHz
t
WL
< 16/fosc: i.e. t
WL
< 1250ns when foscin = 12.8 MHz
t
WU
fr
TX/RX
fp
TX/RX
t
WL
LD
(FC bit = High)
Do
TX/RX
Z
L
(FC bit = Low)
Z
H
Do
TX/RX
TX–PLL section
RX–PLL section
LD output
Locking state / Power saving state
Locking state / Power saving state
Locking state / Power saving state
H
L
L
L
Unlocking state
Unlocking state
Unlocking state
Locking state / Power saving state
Unlocking state
LD Output Logic Table
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