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參數(shù)資料
| 型號： | MB15F02SLPV1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PBCC16 |
| 封裝： | PLASTIC, BCC-16 |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 228K |
| 代理商： | MB15F02SLPV1 |
3
MB15F02SL
I
PIN DESCRIPTIONS
Pin no.
Pin
name
I/O
Descriptions
SSOP-16 BCC-16
1
16
GND
RF
–
Ground for RF-PLL section.
2
1
OSC
IN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
3
2
GND
IF
–
Ground for the IF-PLL section.
4
3
fin
IF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
5
4
V
CCIF
–
Power supply voltage input pin for the IF-PLL section.
6
5
LD/fout
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
7
6
PS
IF
I
Power saving mode control for the IF-PLL section. This pin must be set
at “L” during Power-ON. (Open is prohibited.)
PS
IF
= “H” ; Normal mode
PS
IF
= “L” ; Power saving mode
8
7
Do
IF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
9
8
Do
RF
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
10
9
PS
RF
I
Power saving mode control for the RF-PLL section. This pin must be set
at “L” during Power-ON. (Open is prohibited.)
PS
RF
= “H” ; Normal mode
PS
RF
= “L” ; Power saving mode
11
10
Xfin
RF
I
Prescaler complementary input for the RF-PLL section.
This pin should be grounded via a capacitor.
12
11
V
CCRF
–
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer. When power is OFF, latched data of RF-PLL
is lost.
13
12
fin
RF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
14
13
LE
I
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
15
14
Data
I
Serial data input (with a schmitt trigger input buffer.)
Data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit in
the serial data.
16
15
Clock
I
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F03 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F03L | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F03LPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F03LPV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F03PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
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