- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377878 > MB15E07SL (Fujitsu Limited) Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler(單串行輸入PLL頻率合成器，片內(nèi)2.5 GHz預(yù)定標器) PDF資料下載
參數(shù)資料
| 型號： | MB15E07SL |
| 廠商： | Fujitsu Limited |
| 英文描述： | Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler(單串行輸入PLL頻率合成器，片內(nèi)2.5 GHz預(yù)定標器) |
| 中文描述： | 單串行輸入鎖相環(huán)頻率合成器片的2.5 GHz預(yù)分頻器（單串行輸入鎖相環(huán)頻率合成器，片內(nèi)2.5 GHz的預(yù)定標器） |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 260K |
| 代理商： | MB15E07SL |
MB15E07SL
8
I
FUNCTIONAL DESCRIPTION
1.
Pulse Swallow Function
The divide ratio can be calculated using the following equation:
f
VCO
= [(M
×
N) + A]
×
f
OSC
÷
R (A < N)
f
VCO
: Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0
≤
A
≤
127)
f
OSC
: Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
M
: Preset divide ratio of modulus prescaler (32 or 64)
Serial Data Input
2.
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control bit (CNT)
(1) Shift Register Configuration
Destination of serial data
H
For the programmable reference divider
L
For the programmable divider
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
SW
FC
LDS CS
Programmable Reference Counter
MSB
Data Flow
CNT
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383)
SW
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
FC
: Phase control bit for the phase comparator
LDS
: LD/f
OUT
signal select bit
CS
: Charge pump current select bit
: Control bit
[Table 1]
[Table 2]
[Table 5]
[Table 8]
[Table 7]
[Table 6]
Note: Start data input with MSB first.
LSB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB15E07SR | Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler |
| MB15E07SRPFT | Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler |
| MB15E07SRPV1 | Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler |
| MB15E07 | Serial Input PLL Frequency Synthesizer(串行輸入PLL頻率合成器) |
| MB15F02SLPFV1 | Dual Serial Input PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB15E07SLPFV1 | 制造商:FUJITSU 功能描述:PLL FREQUENCY SYNTHESIZER, 2500 MHZ, PDSO16 |
| MB15E07SLPFV1-G-BND | 制造商:FUJITSU 功能描述: |
| MB15E07SLPFV1-G-BND-6E1 | 功能描述:IC SYNTHESIZER PLL 2.5GHZ 16SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| MB15E07SLPFV1-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB15E07SLPFV1GER6E1 | 制造商:FUJITSU 功能描述:Pb Free |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。