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MAXQ2000
Low-Power LCD Microcontroller
30
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The watchdog timer is controlled through bits in the
WDCN register. Its timeout period can be set to one of
four programmable intervals ranging from 212 to 221
system clocks in its default mode, allowing flexibility to
support different types of applications. The interrupt
occurs 512 system clocks before the reset, allowing the
system to execute an interrupt and place the system in
a known, safe state before the device performs a total
system reset. At 16MHz, watchdog timeout periods can
be programmed from 256s to 33.5s, depending on the
system clock mode.
Serial Peripherals
The microcontroller incorporates several common seri-
al-peripheral interfaces for interconnection with popular
external devices. Multiple formats provide maximum
flexibility and lower cost when designing a system.
UARTs
Serial interfacing is provided through one (-RBX/-RBX+)
or two (-RAX/-RAX+/-RFX/-RFX+) 8051-style universal
synchronous/asynchronous receiver/transmitters. The
UART allows the device to conveniently communicate
with other RS-232 interface-enabled devices, as well as
PCs and serial modems when paired with an external
RS-232 line driver/receiver. The dual independent
UARTs can communicate simultaneously at different
baud rates with two separate peripherals. The UART
can detect framing errors and indicate the condition
through a user-accessible software bit.
The time base of the serial ports is derived from either a
division of the system clock or the dedicated baud
clock generator. The following table summarizes the
operating characteristics as well as the maximum baud
rate of each mode:
1-Wire Bus Master
The MAXQ2000-RAX/-RAX+/-RFX/-RFX+ include a
Dallas Semiconductor 1-Wire bus master, which commu-
nicates to other 1-Wire peripherals, including iButton
products, through a simple bidirectional signaling
scheme over a single electrical connection. The bus
master provides complete control of the 1-Wire bus and
transmit and receive activities, and generates all timing
and
control
sequences
of
the
1-Wire
bus.
Communication between the CPU and the bus master
is achieved through read/write access of the 1-Wire
master address (OWA) and 1-Wire master data (OWD)
peripheral registers. Detailed operation of the 1-Wire
bus is described in the
Book of iButton Standards
(www.maxim-ic.com/iButtonbook).
Serial-Peripheral Interface (SPI) Module
The SPI port is a common, high-speed, synchronous
peripheral interface that shifts a bit stream of variable
length and data rate between the microcontroller and
other peripheral devices. The SPI can be used to com-
municate with other microcontrollers, serial shift regis-
ters, or display drivers. Multiple master and slave
modes permit communication with multiple devices in
the same system. Programmable clock frequency,
character lengths, polarity, and error handling enhance
the usefulness of the peripheral. The maximum baud
rate of the SPI interface is 1/2 the system clock for mas-
ter mode operation and 1/8 the system clock for slave
mode operation.
MODE
TYPE
START BITS
DATA BITS
STOP BIT
MAX BAUD RATE
AT 16MHz
Mode 0
Synchronous
N/A
8
N/A
4Mbps
Mode 1
Asynchronous
1
8
1
500kbps
Mode 2
Asynchronous
1
8 + 1
1
500kbps
Mode 3
Asynchronous
1
8 + 1
1
500kbps
iButton is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated Products, Inc.