參數(shù)資料
型號(hào)： MAXQ1004-B01+
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, QCC16
封裝： 4 X 4 MM, ROHS COMPLIANT, TQFN-16
文件頁(yè)數(shù)： 4/18頁(yè)
文件大?。?/td> 1247K
代理商： MAXQ1004-B01+
MAXQ1004
1-Wire and SPI Authentication Microcontroller
12
Hardware AES Engine
The AES engine is a bidirectional block cipher support-
ing encryption and decryption for all three key lengths
recommended by the National Institute of Standards and
Technology (NIST). Secret keys can be generated by
an on-chip RNG and stored in a predetermined memory
location. The AES engine operates independently of the
processor, except for setting up an operation through
the AES Control register (AESC). The AESC register
provides AES engine operation status and option control.
The AES engine shares the cryptographic memory with
the 1-Wire communications peripheral. Application soft-
ware must ensure that the two peripherals do not access
the cryptographic memory at the same time or data in
the memory may be corrupted. Application software can
interrogate activity bits to ensure that one peripheral
does not interrupt the other. To perform an encryption
or decryption, the keys and data are loaded into the
cryptographic memory and the operation is started with
the appropriate write to the AESC register. Completion
of the operation can be detected by user firmware either
by polling the AESC register or through the use of an
interrupt.
The AES engine displays excellent performance. Based
on key size, the following encryption throughputs are
achieved:
128-bit key size—55 cycles (9.2s at 6MHz)
192-bit key size—70 cycles (12.0s at 6MHz)
256-bit key size—75 cycles (12.5s at 6MHz)
An optional jitter injection feature reduces the effec-
tiveness of differential power analysis (DPA) attacks
against the device. Adding jitter causes random delays
in both the start and ending times of the calculation,
confounding attempts to determine the values in the AES
operation by measuring minute power fluctuations. When
active, the feature adds a variable random delay of 0
to 30 clock cycles to AES calculations. This is accom-
plished by randomly adding 0 to 15 clock cycles before
the AES operation is started, and adding 0 to 15 clock
cycles after the operation is complete.
Watchdog Timer
The watchdog timer functions as the source of both the
timer timeout and the watchdog timer reset. The timeout
period can be programmed in a range of 212 to 229 sys-
tem clock cycles. An interrupt is generated when the time-
out period expires, if the interrupt is enabled. All watchdog
timer resets follow the programmed interrupt timeouts by
512 clock cycles. If the watchdog timer is not restarted
for another full interval in this time period, a system reset
occurs when the reset timeout expires. Table 1 shows
values that demonstrate the various interrupt timeouts
based on an internal clock frequency of 6MHz.
Figure 1. ADC Block Diagram
10-BIT
DELTA-SIGMA
CONVERTER
ADC
CONTROLLER
/2
ADDATA
ADREF
1
0
INTERNAL REFERENCE
AVDD
ADCCLK
ADCONV
ADEN
ADSCL
ADCH
0
1
AN0
TEMP
SENSOR
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參數(shù)描述
MAXQ1004-B01+ 功能描述:16位微控制器 - MCU 1-Wire and SPI Authentication MCU RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT
MAXQ1004-KIT# 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 MAXQ1004 Eval Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類(lèi)型:I2C, SPI, USB 工作電源電壓:
MAXQ1010 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Security Token Microcontroller with RTC and USB
MAXQ1010-A01+ 制造商:Maxim Integrated Products 功能描述:MAXQ1010 PSWD GEN MICRO 48 TQFN - Rail/Tube
MAXQ1010-DNS+ 制造商:Maxim Integrated Products 功能描述:MAXQ1010 PSWD GEN MICRO DIE WAFFLE - Gel-pak, waffle pack, wafer, diced wafer on film
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