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參數(shù)資料
| 型號： | MAX9945AUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP MOS-INPUT LP/LN 8-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 2.2 V/µs |
| 增益帶寬積： | 3MHz |
| 電流 - 輸入偏壓： | 0.05pA |
| 電壓 - 輸入偏移： | 600µV |
| 電流 - 電源： | 400µA |
| 電流 - 輸出 / 通道： | 25mA |
| 電壓 - 電源，單路/雙路(±)： | 4.75 V ~ 38 V，±2.4 V ~ 19 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
MAX9945
38V, Low-Noise, MOS-Input,
Low-Power Op Amp
_______________________________________________________________________________________
3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ROUT = 10k
Ω to GND TA = TMIN to TMAX
VEE +
0.26
VEE +
0.45
Output Voltage Low
VOL
ROUT = 100k
Ω to
GND
TA = TMIN to TMAX
VEE +
0.05
VEE +
0.15
V
ROUT = 10k
Ω to GND TA = TMIN to TMAX
VCC -
0.45
VCC -
0.24
Output Voltage High
VOH
ROUT = 100k
Ω to
GND
TA = TMIN to TMAX
VCC -
0.15
VCC -
0.03
V
AC ELECTRICAL CHARACTERISTICS
Input Current-Noise Density
IN
f = 1kHz
1
fA/
√Hz
Input Voltage Noise
VNP-P
f = 0.1Hz to 10Hz
2
VP-P
f = 100Hz
25
f = 1kHz
16.5
Input Voltage-Noise Density
VN
f = 10kHz
15
nV/
√Hz
Gain Bandwidth
GBW
3
MHz
Slew Rate
SR
2.2
V/s
Capacitive Loading (Note 4)
CLOAD
No sustained oscillations
120
pF
Total Harmonic Distortion
THD
VOUT = 4.5VP-P, AV = 1V/V,
f = 10kHz, ROUT = 10k
Ω to GND
97
dB
POWER-SUPPLY ELECTRICAL CHARACTERISTICS
Power-Supply Voltage Range
VCC - VEE
Guaranteed by PSRR, VEE = 0V
+4.75
+38
V
Power-Supply Rejection Ratio
PSRR
VCC - VEE = +4.75V to +38V
82
100
dB
TA = +25°C
400
700
Quiescent Supply Current
ICC
TA = TMIN to TMAX
850
A
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +15V, VEE = -15V, VIN+ = VIN- = VGND = 0V, ROUT = 100kΩ to GND, TA = -40°C to +125°C, typical values are at TA = +25°C,
unless otherwise noted.) (Note 2)
Note 2: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design.
Note 3: Guaranteed by design. IN+ and IN- are internally connected to the gates of CMOS transistors. CMOS GATE leakage is so
small that it is impractical to test in production. Devices are screened during production testing to eliminate defective units.
Note 4: Specified over all temperatures and process variation by circuit simulation.
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