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參數(shù)資料
| 型號(hào)： | MAX9939AUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 15/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP PGA SPI VOS I/O 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 可編程增益 |
| 電路數(shù)： | 2 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 9 V/µs |
| 增益帶寬積： | 2.15MHz |
| 電流 - 輸入偏壓： | 1pA |
| 電壓 - 輸入偏移： | 1500µV |
| 電流 - 電源： | 3.4mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | 2.9 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
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MAX9939
SPI Programmable-Gain Amplifier
with Input VOS Trim and Output Op Amp
9
Maxim Integrated
SHDN: Set SHDN to 0 for normal operation. Set SHDN
to 1 to place the device in a low-power 13A shutdown
mode. In shutdown mode, the outputs OUTA and OUTB
are high impedance, however, the SPI decode circuitry
is still active. Each instruction requires a write to the
SHDN bit.
MEAS: The MAX9939 provides a means for measuring
its own input offset voltage. When MEAS is set to 1, the
INA- input is disconnected from the input signal path
and internally shorted to INA+. This architecture thus
allows the input common-mode voltage to be compen-
sated at the application-specific input common-mode
voltage of interest. The input offset voltage of the PGA
is the output offset voltage divided by the programmed
gain without any VOS trim (i.e., V3:V0 set to 0):
VOS-INHERENT = (VOUTA - VCC/2)/Gain
Program VOS to offset VOS-INHERENT. The input VOS
also includes the effect of mismatches in the resistor-
dividers. Setting MEAS to 0 switches the inputs back to
the signals on INA+ and INA-. Each instruction requires
a write to the MEAS bit.
Programming Gain
The PGA’s gain is set by the bits G3:G0 in the Gain reg-
ister. Table 3 shows the relationship between the bits
G3:G0 and the amplifier’s gain. The slew rate and
small-signal bandwidth (SSBW) of the PGA depend on
its gain setting as shown in Table 3.
Programming Input Offset Voltage (VOS)
The input offset voltage is set by the bits V4:V0 in the
Input Offset Voltage Trim register. Bit V4 determines the
polarity of the offset. Setting V4 to 0 makes the offset
positive, while setting V4 to 1 makes the offset negative.
Table 4 shows the relationship between V3:V0 and VOS.
To determine the effect of VOS at the output of the ampli-
fier for gains other than 1, use the following formula:
VOUTA = VCC/2 + Gain x (VOS-INHERENT + VOS)
where VOS-INHERENT is the inherent input offset voltage
of the amplifier, which can be measured by setting
MEAS to 1.
Applications Information
Use of Output Amplifier as Active Filter
The output amplifier can be configured as a multiple-
feedback active filter as shown in Figure 3, which tradi-
tionally has better stopband attenuation characteristics
than Sallen-Key filters. These filters also possess inher-
ently better distortion performance since there are no
common-mode induced effects (i.e., the common-
mode voltage of the operational amplifier is always
fixed at VCC/2 instead of it being signal dependent
such as in Sallen-Key filters). Choose external resistors
and capacitors to create lowpass, bandpass, or high-
pass filters.
G3:G0
GAIN
(V/V)
SLEW RATE
(V/s)
SMALL-SIGNAL BANDWIDTH (MHz)
0000
1
2.90
2.15
0001
10
8.99
2.40
0010
20
8.70
1.95
0011
30
12.80
3.40
0100
40
12.50
2.15
0101
60
13.31
2.60
0110
80
12.15
1.91
0111
120
18.53
2.30
1000
157
16.49
1.78
0.2 (VCC = 5V)
1001
0.25 (VCC = 3.3V)
2.86
1.95
1010
1
2.90
2.15
Table 3. Gain
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