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參數資料
| 型號： | MAX9850ETI+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 26/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUDIO .095W STER 28TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 60 |
| 系列： | DirectDrive® |
| 類型： | AB 類 |
| 輸出類型： | 耳機，2-通道（立體聲） |
| 在某負載時最大輸出功率 x 通道數量： | 95mW x 2 @ 16 歐姆 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 特點： | DAC，消除爆音，數字輸入，I²C，I²S，線路級輸入和輸出，靜音，關機，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應商設備封裝： | 28-TQFN-EP（5x5） |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 包裝： | 管件 |
| 產品目錄頁面： | 1392 (CN2011-ZH PDF) |
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MAX9850
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9850’s
slave address with the R/
W bit set to 0 followed by the
register address. A REPEATED START condition is then
sent followed by the slave address with the R/
W bit set
to 1. The MAX9850 transmits the contents of the speci-
fied register. The address pointer autoincrements after
transmitting the first byte. Attempting to read from reg-
ister addresses higher than 0xB results in repeated
reads of 0xB. Note that 0xB is a reserved register.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not-
acknowledge from the master and then a STOP condi-
tion. Figure 10 illustrates the frame format for reading
one byte from the MAX9850. Figure 11 illustrates the
frame format for reading multiple bytes from the
MAX9850.
Applications Information
Powering On/Off the MAX9850
The MAX9850 powers on in low-power shutdown mode
with the DAC, headphones, line inputs, and outputs all
disabled. For useful circuit operation to be available,
the charge pump needs to be activated using
CPEN(1:0) in the enable register (register 0x5, bits B5
and B4). Setting the appropriate bits in the enable reg-
ister will enable the desired circuit functions on the
MAX9850. Finally, the global shutdown bit,
SHDN
needs to be set to 1 (register 0x5, bit B7). The enable
bits can all be set with a single I2C write operation.
It is good practice for an application to configure the
I2C registers before taking the MAX9850 out of shut-
down. This may include setting initial volume levels,
DAC mode of operation, stereo or mono operation, and
audio interface settings. Powering on the MAX9850 with
all the registers set ensures that the audio output will
not be interrupted.
The charge pump starts and establishes the internal
supply voltages once the appropriate byte is written to
the enable register. The MAX9850 is ready for opera-
tion approximately 10ms after the charge pump is
enabled. If selected, the headphone outputs will also
complete a clickless/popless power-up sequence dur-
ing this time. The headphone amplifier status bit (SHP)
(register 0x1, bit B3) sets to 1 once the headphones
are ready to operate. The line inputs and outputs will
also turn on during this 10ms startup period if enabled.
Let AC-coupling capacitors settle before enabling the line
input amplifiers. The input-coupling capacitor charges to
the output bias voltage of the driving device even while
the MAX9850 is in shutdown. The input AC coupling
capacitors are charged and ready for use immediately
after power is applied to the system in most applications.
Stereo Audio DAC with DirectDrive
Headphone Amplifier
32
______________________________________________________________________________________
ACKNOWLEDGE FROM MAX9850
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9850
NOT ACKNOWLEDGE FROM MASTER
B1 B0
B3 B2
B5 B4
B7 B6
A
P
A
0
ACKNOWLEDGE FROM MAX9850
R/W
SA
R/W
REPEATED START
Sr
1
SLAVE ADDRESS
REGISTER ADDRESS
SLAVE ADDRESS
DATA BYTE
Figure 10. Reading One Byte of Data from MAX9850
ACKNOWLEDGE FROM MAX9850
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9850
ACKNOWLEDGE FROM MASTER
B1 B0
B3 B2
B5 B4
B7 B6
A
0
ACKNOWLEDGE FROM MAX9850
R/W
SA
R/W
REPEATED START
Sr
1
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
NOT ACKNOWLEDGE
FROM MASTER
B1 B0
B3 B2
B5 B4
B7 B6
P
A
SLAVE ADDRESS
REGISTER ADDRESS
SLAVE ADDRESS
FIRST DATA BYTE
Nth DATA WORD
Figure 11. Reading n-Bytes from MAX9850
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MAX9850ETI+ | 功能描述:音頻數/模轉換器 IC Stereo Audio DAC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| MAX9850ETI+G47 | 功能描述:音頻數/模轉換器 IC Stereo Audio DAC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| MAX9850ETI+T | 功能描述:音頻數/模轉換器 IC Stereo Audio DAC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| MAX9850ETI+TG47 | 功能描述:音頻數/模轉換器 IC Stereo Audio DAC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| MAX9850ETI-T | 制造商:Maxim Integrated Products 功能描述:STEREO AUDIO DAC WITH DIRECTDRIVE HEADPHONE A - Tape and Reel |
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