參數(shù)資料
型號(hào)： MAX9850
廠商： Maxim Integrated Products, Inc.
英文描述： Stereo Audio DAC with DirectDrive Headphone Amplifier
中文描述： 立體聲音頻DAC，帶有DirectDrive®耳機(jī)放大器
文件頁(yè)數(shù)： 12/36頁(yè)
文件大?。?/td> 956K
代理商： MAX9850
M
Stereo Audio DAC with DirectDrive
Headphone Amplifier
12
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
LRCLK
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock and determines
whether the audio data on SDIN is routed to the left or right channel. LRCLK is an input when the
MAX9850 is in slave mode and an output when in master mode.
2
BCLK
Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9850 is in slave mode and an
output when in master mode.
3
4
5
6
SDIN
DV
DD
MCLK
DGND
Digital Audio Serial Data Input
Digital Power-Supply Input. Bypass to DGND with a 1μF ceramic capacitor.
Master Clock Input. All internal digital clocks are derived from MCLK.
Digital Ground
I
2
C Address-Select Input. Connect to AGND, AV
DD
, or SDA to select one of the three possible I
2
C
addresses.
7
ADD
8
GPIO
General-Purpose Input/Output. Configure GPIO as an input or an output through the GPIO register.
GPIO can perform the function of an interrupt when configured as an output. See the
GPIO
section.
9
10
11
12
13
14
15
16
17
18
19
20
INR
INL
OUTR
OUTL
REF
AGND
NREG
PREG
AV
DD
HPR
HPL
SV
SS
Right-Channel Line Input. INR is mixed with the right DAC output.
Left-Channel Line Input. INL is mixed with the left DAC output.
Line Level Right-Channel Output. OUTR is biased at AGND.
Line Level Left-Channel Output. OUTL is biased at AGND.
Reference Output. Bypass to AGND with a 1μF ceramic capacitor.
Analog Ground
Line Output Negative Regulator Output. Bypass to AGND with a 1μF capacitor.
Line Output Positive Regulator Output. Bypass to AGND with a 1μF capacitor.
Analog Power Supply. Bypass to AGND with a 1μF ceramic capacitor.
Right-Channel Headphone Output. HPR is a DirectDrive output biased at AGND.
Left-Channel Headphone Output. HPL is a DirectDrive output biased at AGND.
Headphone Amplifier Negative Power-Supply Input. Connect to PV
SS
.
Headphone Sense Input. Connect to the control pin of a headphone jack for automatic headphone
sensing. Float HPS if unused. See the
Headphone Sense Input
section.
21
HPS
22
PV
SS
Inverting Charge-Pump Output. Bypass to PGND with a 2.2μF ceramic capacitor and connect to SV
SS
to provide the headphone amplifiers with a negative supply.
23
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47μF ceramic capacitor between
C1N and C1P.
24
PGND
Charge-Pump Ground
25
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47μF ceramic capacitor between C1P
and C1N.
26
PV
DD
Charge-Pump and Headphone Amplifier Positive Power-Supply Input. Bypass to PGND with a 1μF
ceramic capacitor. Connect to AV
DD
for normal operation.
I
2
C-Compatible Serial Clock Input
I
2
C-Compatible Serial Data Input/Output
Exposed Thermal Pad. Connect EP to AGND.
27
28
—
SCL
SDA
EP
相關(guān)PDF資料
PDF描述
MAX9850ETI Stereo Audio DAC with DirectDrive Headphone Amplifier
MAX9995ETX-D Dual, SiGe, High-Linearity, 1700MHz to 2200MHz Downconversion Mixer with LO Buffer/Switch
MAX9995ETX-T Dual, SiGe, High-Linearity, 1700MHz to 2200MHz Downconversion Mixer with LO Buffer/Switch
MAX9995ETX-TD Dual, SiGe, High-Linearity, 1700MHz to 2200MHz Downconversion Mixer with LO Buffer/Switch
MAX9995ETX Dual, SiGe, High-Linearity, 1700MHz to 2200MHz Downconversion Mixer with LO Buffer/Switch
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