Charge Pump
The MAX9770 features a low-noise charge pump. The
switching frequency of the charge pump is 1/2 the
switching frequency of the Class D amplifier, regardless
of the operating mode. When SYNC is driven externally,
the charge pump switches at 1/2 fSYNC. When SYNC =
VDD, the charge pump switches with a spread-spectrum
pattern. The nominal switching frequency is well beyond
the audio range, and thus does not interfere with the
audio signals, resulting in an SNR of 101dB. The switch
drivers feature a controlled switching speed that mini-
mizes noise generated by turn-on and turn-off tran-
sients. By limiting the switching speed of the charge
pump, the di/dt noise caused by the parasitic bond wire
and trace inductance is minimized. Although not typical-
ly required, additional high-frequency noise attenuation
can be achieved by increasing the size of C2 (see the
Block Diagram). The charge pump is active in both
speaker and headphone modes.
Input Multiplexer/Mixer
The MAX9770 features an input multiplexer/mixer that
allows multiple audio sources to be selected/mixed.
Driving a SEL_ input high selects the input channel (see
Table 2), and the audio signal is output to the active
amplifier. When a stereo path is selected in speaker
mode, the left and right inputs are attenuated by 6dB and
mixed together, resulting in a true mono reproduction of a
stereo signal. When more than one signal path is select-
ed, the sources are attenuated before mixing to preserve
overall amplitude. For example, selecting two sources in
headphone mode results in 6dB attenuation of the inputs,
while selecting three sources in headphone mode results
in 9.5dB attenuation of the inputs. Table 2 shows how the
input signals are attenuated and mixed for each possible
input selection combination.
Headphone Sense Input (HPS)
The headphone sense input (HPS) monitors the head-
phone jack, and automatically configures the device
based upon the voltage applied at HPS. A voltage of
less than 0.8V sets the device to speaker mode. A volt-
age of greater than 2V disables the bridge amplifiers
and enables the headphone amplifiers.
For automatic headphone detection, connect HPS to the
control pin of a 3-wire headphone jack as shown in
Figure 6. With no headphone present, the output imped-
ance of the headphone amplifier pulls HPS to less than
0.8V. When a headphone plug is inserted into the jack,
the control pin is disconnected from the tip contact and
HPS is pulled to VDD through the internal 800k
Ω pullup.
When driving HPS from an external logic source, ground
HPS when the MAX9770 is shut down. Place a 10k
Ω
resistor in series with HPS and the headphone jack to
ensure ±8kV ESD protection.
BIAS
The MAX9770 features internally generated, power-sup-
ply independent, common-mode bias voltages refer-
enced to GND. BIAS provides both click-and-pop
suppression and sets the DC bias level for the amplifiers.
Choose the value of the bypass capacitor as described in
the
BIAS Capacitor section. No external load should be
applied to BIAS. Any load lowers the BIAS voltage, affect-
ing the overall performance of the device.
Gain Selection
The MAX9770 features logic-selectable, internally set
gains. GAIN1 and GAIN2 set the gain of the MAX9770
speaker and headphone amplifiers as shown in Table 3.
The MAX9770 can be configured to automatically
switch between two gain settings depending on
whether the device is in speaker or headphone mode.
By driving one or both gain inputs with HPS, the gain of
MAX9770
1.2W, Low-EMI, Filterless, Mono Class D Amplifier
with Stereo DirectDrive Headphone Amplifiers
______________________________________________________________________________________
15
Table 2. MAX9770 Multiplexer/Mixer Settings
HEADPHONE MODE
SEL1
SEL2
SELM
HPOUTL
HPOUTR
SPEAKER MODE
0
MUTE
1
0
IN1L
IN1R
(IN1L + IN1R) / 2
0
1
0
IN2L
IN2R
(IN2L + IN2R) / 2
0
1
MONO
1
0
(IN1L + IN2L) / 2
(IN1R + IN2R) / 2
(IN1L + IN1R + IN2L + IN2R) / 4
1
0
1
(IN1L + MONO) /2
(IN1R + MONO) / 2
(IN1L + IN1R + MONO x 2) / 4
0
1
(IN2L + MONO) / 2
(IN2R + MONO) / 2
(IN2L + IN2R + MONO x 2) / 4
11
1
(IN1L + IN2L + MONO) / 3
(IN1R + IN2R + MONO) / 3
(IN1L + IN1R + IN2L + IN2R + MONO x 2) / 6