參數(shù)資料
型號(hào): MAX9736DETJ+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/25頁
文件大小: 0K
描述: IC AMP CLASS D HIGH PWR 32TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: D 類
輸出類型: 1-通道(單聲道)或 2-通道(立體聲)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 17mW x 1 @ 4 歐姆; 8.5mW x 2 @ 8 歐姆
電源電壓: 8 V ~ 28 V
特點(diǎn): 消除爆音,靜音,短路保護(hù)和熱保護(hù),關(guān)機(jī)
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
封裝/外殼: 32-WFQFN 裸露焊盤
包裝: 帶卷 (TR)
MAX9736
Mono/Stereo High-Power Class D Amplifier
______________________________________________________________________________________
17
Internal Regulator
The MAX9736 features an internal 5V regulator, VS,
powered from PVDD. Connect REGEN to SHDN so that
the internal 5V regulator is enabled/disabled when the
MAX9736 is enabled/disabled. If an external 5V supply
is available, drive REGEN low and connect external 5V
supply to VS to minimize the power dissipation of the
MAX9736.
Supply Bypassing,
Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. Use wide traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Proper grounding improves
audio performance, minimizes crosstalk between chan-
nels, and prevents switching noise from coupling into
the audio signal. Connect PGND and AGND together at
a single point on the PCB. Route all traces that carry
switching transients away from AGND and the
traces/components in the audio signal path.
Bypass each PVDD pin with a 0.1μF capacitor to PGND.
Place the bypass capacitors as close as possible to the
MAX9736. Place a 220μF capacitor between PVDD and
PGND. Bypass VS with a 1μF capacitor to AGND.
Use wide, low-resistance output traces. Current drawn
from the outputs increases as load impedance
decreases. High-output trace resistance decreases the
power delivered to the load. The MAX9736 TQFN pack-
age features an exposed thermal paddle on its under-
side. This paddle lowers the package’s thermal
resistance by providing a heat conduction path from
the die to the PCB. Connect the exposed thermal pad
to PGND by using a large pad and multiple vias to the
PGND plane.
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