Detailed Description
The MAX9723 stereo headphone amplifier features
Maxim’s DirectDrive architecture, eliminating the large
output-coupling capacitors required by conventional sin-
gle-supply headphone amplifiers. The MAX9723 consists
of two 62mW Class AB headphone amplifiers, hard-
ware/software shutdown control, inverting charge pump,
integrated 32-level volume control, BassMax circuitry,
comprehensive click-and-pop suppression circuitry, and
an I2C-compatible interface (see the Functional
Diagram/Typical Operating Circuit). A negative power
supply (PVSS) is created internally by inverting the posi-
tive supply (VDD). Powering the amplifiers from VDD and
PVSS increases the dynamic range of the amplifiers to
almost twice that of other single-supply amplifiers,
increasing the total available output power.
The MAX9723 DirectDrive outputs are biased at SGND
(see Figure 1). The benefit of this 0V bias is that the
amplifier outputs do not have a DC component, elimi-
nating the need for large DC-blocking capacitors.
Eliminating the DC-blocking capacitors on the output
saves board space, system cost, and improves low-fre-
quency response.
An I2C-compatible interface allows serial communica-
tion between the MAX9723 and a microcontroller. The
MAX9723 is available with two different I2C addresses
allowing two MAX9723 ICs to share the same bus (see
Table 1). The internal command register controls the
shutdown status of the MAX9723, enables the BassMax
circuitry, sets the maximum gain of the amplifier, and
sets the volume level (see Table 2). The MAX9723’s
BassMax circuitry improves audio reproduction by
boosting the bass response of the amplifier, compen-
sating for any low-frequency attenuation introduced by
MAX9723
Stereo DirectDrive Headphone Amplifier
with BassMax, Volume Control, and I2C
_______________________________________________________________________________________
9
Pin Description
PIN
BUMP
THIN QFN
UCSP
NAME
FUNCTION
1D1
VDD
Power-Supply Input. Bypass VDD to PGND with a 1F capacitor.
2
C1
C1P
Charge-Pump Flying Capacitor Positive Terminal
3
B1
PGND
Power Ground. Connect to SGND.
4
A1
C1N
Charge-Pump Flying Capacitor Negative Terminal
5
B2
SCL
Serial Clock Input. Connect a 10k
Ω pullup resistor from SCL to VDD.
6A2
PVSS
Charge-Pump Output. Connect to SVSS. Bypass PVSS with a 1F capacitor
to PGND.
7
A3
SDA
Serial-Data Input. Connect a 10k
Ω pullup resistor from SDA to VDD.
8B3
SHDN
Shutdown. Drive SHDN low to disable the MAX9723. Connect SHDN to VDD while bit 7
is high for normal operation (see the Command Register section).
9
A4
SGND
Signal Ground. Connect to PGND.
10
B4
INL
Left-Channel Input
11
C4
INR
Right-Channel Input
12
D4
SVSS
Headphone Amplifier Negative Power-Supply Input. Connect to PVSS.
13
C3
BBR
Right BassMax Input. Connect an external lowpass filter between OUTR and BBR to
apply bass boost to the right-channel output. Connect BBR to SGND if BassMax is not
used (see the BassMax (Bass Boost) section).
14
D3
OUTR
Right Headphone Output
15
D2
OUTL
Left Headphone Output
16
C2
BBL
Left BassMax Input. Connect an external lowpass filter between OUTL and BBL to
apply bass boost to the left-channel output. Connect BBL to SGND if BassMax is not
used (see the BassMax (Bass Boost) section).
EP
—
EP
Exposed Paddle. Connect EP to SVSS or leave unconnected.