參數(shù)資料
型號: MAX9723DETE+
廠商: Maxim Integrated Products
文件頁數(shù): 4/25頁
文件大?。?/td> 0K
描述: IC AMP AUDIO .06W STER AB 16TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 75
系列: DirectDrive®
類型: AB 類
輸出類型: 耳機(jī),2-通道(立體聲)
在某負(fù)載時最大輸出功率 x 通道數(shù)量: 60mW x 2 @ 16 歐姆
電源電壓: 1.8 V ~ 3.6 V
特點: 低音增強模式,消除爆音,I²C,靜音,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(4x4)
封裝/外殼: 16-WQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 1392 (CN2011-ZH PDF)
配用: MAX9723DEVKIT+-ND - EVALUATION KIT FOR MAX9723
MAX9723
from the master. The master, typically a microcontroller,
generates SCL and initiates data transfer on the bus.
A master device communicates to the MAX9723 by
transmitting the proper address followed by the data
word. Each transmit sequence is framed by a START (S)
or REPEATED START (Sr) condition and a STOP (P) con-
dition. Each word transmitted over the bus is 8 bits long
and is always followed by an acknowledge clock pulse.
The MAX9723 SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500
Ω, is required on the SDA bus. The MAX9723 SCL
line operates as an input only. A pullup resistor, greater
than 500
Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the master in a single-master sys-
tem has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. Series resistors
protect the digital inputs of the MAX9723 from high-
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
Start and Stop Conditions
SDA and SCL idle high when the bus is not in use. A
master device initiates communication by issuing a
START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure
4). A START condition from the master signals the begin-
ning of transmission to the MAX9723. The master termi-
nates transmission and frees the bus by issuing a STOP
condition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9723 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Slave Address
The MAX9723 is available with one of two preset slave
addresses (see Table 1). The address is defined as the
seven most significant bits (MSBs) followed by the
Read/Write (R/W) bit. The address is the first byte of
information sent to the MAX9723 after the START condi-
tion. The MAX9723 is a slave device only capable of
being written to. The sent R/W bit must always be a
zero when configuring the MAX9723.
The MAX9723 acknowledges the receipt of its address
even if R/W is set to 1. However, the MAX9723 will not
drive SDA. Addressing the MAX9723 with R/W set to 1
causes the master to receive all 1’s regardless of the
contents of the command register.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9723 uses to handshake receipt of each byte of
Stereo DirectDrive Headphone Amplifier
with BassMax, Volume Control, and I2C
12
______________________________________________________________________________________
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
tHD, STA
tSU, STA
tHD, STA
tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tR
tF
Figure 3. 2-Wire Serial-Interface Timing Diagram
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MAX9723DETE+T 功能描述:音頻放大器 Stereo DirectDrive Headphone Amplifier RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel
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