參數(shù)資料
型號(hào): MAX97001EWP+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 26/37頁(yè)
文件大小: 0K
描述: IC AUDIO SUBSYSTEM 20WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: DirectDrive®
類型: D 類
輸出類型: 1-通道(單聲道),帶立體聲耳機(jī)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 920mW x 1 @ 8 歐姆; 37mW x 2 @ 16 歐姆
電源電壓: 2.7 V ~ 5.5 V
特點(diǎn): 消除爆音,差分輸入,I²C,靜音,關(guān)閉,音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 20-WLP
封裝/外殼: 20-WFBGA,WLBGA
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX97001EWP+TDKR
Audio Subsystem with Mono Class D Speaker
and Class H Headphone Amplifiers
MAX97001
32
Figure 10. Writing One Byte of Data to the MAX97001
Figure 11. Writing n-Bytes of Data to the MAX97001
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate
a read operation. The MAX97001 acknowledges receipt
of its slave address by pulling SDA low during the 9th
SCL clock pulse. A START command followed by a read
command resets the address pointer to register 0x00.
The first byte transmitted from the MAX97001 is the con-
tents of register 0x00. Transmitted data is valid on the
rising edge of SCL. The address pointer autoincrements
after each read data byte. This autoincrement feature
allows all registers to be read sequentially within one
continuous frame. A STOP condition can be issued after
any number of read data bytes. If a STOP condition is
issued followed by another read operation, the first data
byte to be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX97001’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START condition is then
sent followed by the slave address with the R/W bit set
to 1. The MAX97001 then transmits the contents of the
specified register. The address pointer autoincrements
after transmitting the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowl-
edge from the master and then a STOP condition. Figure
12 illustrates the frame format for reading one byte from
the MAX97001. Figure 13 illustrates the frame format for
reading multiple bytes from the MAX97001.
A
0
SLAVE ADDRESS
REGISTER ADDRESS
DATA BYTE
ACKNOWLEDGE FROM MAX97001
R/W
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX97001
B1
B0
B3
B2
B5
B4
B7
B6
S
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX97001
B1 B0
B3 B2
B5 B4
B7 B6
A
0
ACKNOWLEDGE FROM MAX97001
R/W
S
A
1 BYTE
ACKNOWLEDGE FROM MAX97001
B1 B0
B3 B2
B5 B4
B7 B6
P
A
SLAVE ADDRESS
REGISTER ADDRESS
DATA BYTE 1
DATA BYTE n
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