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參數(shù)資料
| 型號： | MAX9492ETP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | XO, clock |
| 英文描述： | Multiple-Output Clock Generator with Spread Spectrum |
| 中文描述： | 133 MHz, OTHER CLOCK GENERATOR, QCC20 |
| 封裝： | 5 X 5 MM, 0.80 MM HEIGHT, MO-220WHHC, TQFN-20 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 276K |
| 代理商： | MAX9492ETP |
M
Multiple-Output Clock Generator
with Spread Spectrum
_______________________________________________________________________________________
9
Reading from the MAX9492
Reading from the MAX9492 registers begins with a
START condition and a device address with the write bit
set low, then the register address that is to be read, fol-
lowed by a repeated START condition and a device
address with the write bit set high, and finally the data
are shifted out (Figure 3). Following a START condition,
the first 7 bits comprise the device address. The 8th bit
is low to indicate a write operation (to write in the follow-
ing register address). An acknowledge bit is then gener-
ated by the MAX9492, signaling that it recognizes its
address. The next 8 bits form the register address, indi-
cating the location of the data to be read, followed by
another acknowledge, again generated by the
MAX9492. The master then produces a repeated START
condition and readdresess the device, with the R/
W
bit
high to indicate a read operation (Figure 3). The
MAX9492 generates an acknowledge bit, signaling that it
recognizes its address. The data byte is then clocked
out of the MAX9492. A final not-acknowledge bit, gener-
ated by the master (not required), and a STOP condition,
also generated by the master, complete the communica-
tion. To read from the device again, the entire read pro-
cedure is repeated; I
2
C burst-read mode is not
supported by the MAX9492.
Device Control Registers
The MAX9492 has eight control registers. The register
addresses and functions are shown in Table 2. The first
seven registers are used to set the six outputs, with
register 0x00 controlling all outputs simultaneously, and
the rest are mapped to individual outputs. All other
addresses are reserved and are not to be used.
REGISTER
ADDRESS
OUTPUT PORT
00
01
02
03
04
05
06
Broadcast to all CLK registers
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
Reserved
All others
Table 2. Register Address Mapping
1
1
A4
A3
A2
A1
A0
S
ACK
DEVICE ADDRESS
START
RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK
REGISTER ADDRESS
RA7
D7
D6
D5
D4
D3
D2
D1
ACK
D0
P
DATA IN
STOP
MASTER-WRITE DATA STRUCTURE
1
1
A4
A3
A2
A1
A0
0
S
ACK
DEVICE ADDRESS
START
RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK
REGISTER ADDRESS
RA7
RS
1
1
A4
A3
A2
A1
ACK
A0
1
DEVICE ADDRESS
STOP
MASTER-READ DATA STRUCTURE
D7
D6
D5
D4
D3
D2
ACK
P
D0
D1
ACK = ACKNOWLEDGE
ACK = NOT-ACKNOWLEDGE
S = START CONDITION
A_ = DEVICE ADDRESS
P = STOP CONDITION
RS = REPEATED START
RA_ = REGISTER ADDRESS
D_ = DATA
DATA OUT
R/W
R/W
R/W
0
= MASTER TO SLAVE
= SLAVE TO MASTER
DATA DIRECTION
Figure 3. I
2
C Interface Data Structure
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| MAX9492ETP+ | 功能描述:鎖相環(huán) - PLL Multiple-Output Clock Generator with Spread Spectrum RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9492ETP+T | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9492ETP-T | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9500EEE+ | 功能描述:視頻 IC 3Ch HDTV Filter RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MAX9500EEE+T | 功能描述:視頻 IC 3Ch HDTV Filter RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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