參數(shù)資料
型號: MAX9380ESA+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 編、解碼器及復(fù)用、解復(fù)用
英文描述: 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8
封裝: 0.150 INCH, EXPOSED PAD, SOIC-8
文件頁數(shù): 6/8頁
文件大?。?/td> 166K
代理商: MAX9380ESA+
MAX9380
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
6
_______________________________________________________________________________________
Detailed Description
The MAX9380 is a high-speed, low-jitter 2:1 multiplexer
designed for clock and data distribution. The device
selects one of the two single-ended inputs.
The multiplexer function is controlled by the single-
ended SEL input. A high level on the SEL input selects
the single-ended data input Da. Similarly, a low level on
the SEL input selects the single-ended data input Db.
The selected input is converted to a differential signal
at the Q and Q outputs.
The inputs Da, Db, and SEL have a 75k
pulldown to
VEE. This ensures that an open input has a low state. All
inputs can be driven from a single-ended LVECL/
LVPECL signal or to VEE and VCC.
Applications Information
LVECL/LVPECL
In LVECL systems, the positive supply voltage is con-
ventionally chosen to be system ground. This arrange-
ment produces the best noise immunity since ground is
normally a system-wide reference voltage. Operate the
MAX9380 with VCC = 0 (ground) and VEE = -3.3V for an
LVECL system.
The MAX9380 operates in LVPECL systems by con-
necting VEE to ground and VCC to a positive supply
voltage. Connect VCC = +3.3V and VEE = 0 for an
LVPECL system.
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to
maximize the performance and noise immunity. This is
particularly true of use in an LVPECL system where the
power-supply voltage is used as a reference. Bypass
VCC to VEE with high-frequency surface-mount ceramic
0.1F and 0.01F capacitors in parallel as close to the
device as possible, with the 0.01F capacitor closest to
the device pins. Use multiple parallel vias for ground
plane connection to minimize inductance.
Circuit Board Traces
Input and output trace characteristics affect the perfor-
mance of ECL devices. Connect each of the MAX9380
inputs and outputs to a 50
characteristic impedance
trace. Avoid discontinuities in differential impedance
and maximize common-mode noise immunity by main-
taining the distance between differential traces and
avoid sharp corners. Minimize the number of vias to
prevent impedance discontinuities. Reduce reflections
by maintaining the 50
characteristic impedance
through connectors and across cables. Minimize skew
by matching the electrical length of the traces.
Output Termination
Terminate outputs through 50
to VCC - 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if the Q output of the MAX9380 is
connected to a single-ended input, terminate both the
Q and Q outputs.
Figure 2. Select Input-to-Output Propagation Delay and Transition Timing Diagram
Da = HIGH
Db = LOW
SEL
SINGLE-ENDED WAVEFORMS
50%
tPLH2
tPHL2
VIH
VIL
VOH
VOL
Q
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