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參數(shù)資料
| 型號： | MAX9321EUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA DRIVER 1:1 8-UMAX |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/數(shù)據(jù)驅動器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVECL，LVPECL |
| 輸出： | LVECL，LVPECL |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | 2.25 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50
±1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE. Typical
values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 8, 11)
-40
°C
+25
°C
+85
°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Added
Deterministic
Jitter (Note 10)
tDJ
3.0Gbps
223 -1 PRBS pattern
57
80
57
80
57
80
ps
(p-p)
VOH - VOL
≥ 300mV,
Clock pattern,
Figure 2
3.0
Switching
Frequency
fMAX
VOH - VOL
≥ 550mV,
Clock pattern,
Figure 2
2.0
GHz
Output Rise/
Fall Time
(20% to 80%)
tR, tF
Figure 2
50
88
120
50
89
120
50
90
120
ps
Note 1: Guaranteed by design and characterization.
Note 2: Measurements are made with the device in thermal equilibrium.
Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 4: DC parameters production tested at TA = +25°C. Guaranteed by design and characterization over the full operating temp-
erature range.
Note 5: Single-ended input operation is limited to VCC - VEE
≥ 3.0V.
Note 6: Use VBB as a reference for inputs on the same device only.
Note 7: All pins open except VCC and VEE.
Note 8: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 10: Device jitter added to the input signal.
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| MAX9322ECY+ | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL DIVIDE-BY-1/DIVIDE-BY-2 CLOCK DRVR 52TQFP - Rail/Tube |
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