參數(shù)資料
型號(hào)： MAX9257GCM/V+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 33/52頁(yè)
文件大?。?/td> 0K
描述： IC SER/DESER PROG 48-LQFP
其它有關(guān)文件： Automotive Product Guide
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 250
功能： 串行器/解串器
數(shù)據(jù)速率： 840Mbps
輸入類(lèi)型： 串行
輸出類(lèi)型： LVDS
輸入數(shù)： 16
輸出數(shù)： 1
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤(pán)
MAX9257/MAX9258
______________________________________________________________________________________
39
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
the LVDS driver termination resistor (RTD), and the series
AC-coupling capacitors (C). The RC time constant for
four equal-value series capacitors is (C x (RTD + RTR))/4.
RTD and RTR are required to match the transmission line
impedance (usually 100Ω). This leaves the capacitor
selection to change the system time constant. In the fol-
lowing example, the capacitor value for a droop of 2% is
calculated:
where:
C = AC-coupling capacitor (F)
tB = bit time(s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
RTD = driver termination resistor (Ω)
RTR = receiver termination resistor (Ω)
The bit time (tB) is the serial-clock period or the period
of the pixel clock divided by the total number of bits.
The maximum DSV for the MAX9257 encoding equals
to the total number of bits transmitted in one pixel clock
cycle. This means that tB x DSV ≤ tT.
The capacitor for 2% maximum droop at 16MHz paral-
lel rate clock is:
Total number of bits is = 10 (data) + 2 (HSYNC and
VSYNC) + 2 (encoding) + 2 (parity) = 16
C ≥ 0.062F
Jitter due to droop is proportional to the droop and tran-
sition time:
tJ = tTT x D
where:
tJ = jitter(s)
tTT = transition time(s) (0 to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
tJ = 1ns x 0.02
tJ = 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter. Use
high-frequency, surface-mount ceramic capacitors.
Power-Supply Circuits and Bypassing
All single-ended inputs and outputs on the MAX9257
are powered from VCCIO. All single-ended outputs on
the MAX9258 are powered from VCCOUT. VCCIO and
VCCOUT can be connected to a +1.71V to +3.6V sup-
ply. The input levels or output levels scale with these
supply rails.
Board Layout
Separate the LVCMOS/LVTTL signals and LVDS signals
to prevent crosstalk. A four-layer PCB with separate lay-
ers for power, ground, LVDS, and digital signals is rec-
ommended. Layout PCB traces for 100Ω differential
characteristic impedance. The trace dimensions
depend on the type of trace used (microstrip or
stripline). Note that two 50Ω PCB traces do not have
100Ω differential impedance when brought close
together—the impedance goes down when the traces
are brought closer.
Route the PCB traces for an LVDS channel (there are
two conductors per LVDS channel) in parallel to main-
tain the differential characteristic impedance. Place the
100Ω (typ) termination resistor at both ends of the
LVDS driver and receiver. Avoid vias. If vias must be
used, use only one pair per LVDS channel and place
the via for each line at the same point along the length
of the PCB traces. This way, any reflections occur at
the same time. Do not make vias into test points for
ATE. Make the PCB traces that make up a differential
pair the same length to avoid skew within the differen-
tial pair.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables offer superior signal quality compared to ribbon
cable and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise
as common mode that is rejected by the LVDS receiver.
C
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tDSV
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX9257GTL/V+ 功能描述:串行器/解串器 - Serdes Prog Serializer / Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9257GTL/V+T 功能描述:串行器/解串器 - Serdes Prog Serializer / Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9257GTL+ 功能描述:串行器/解串器 - Serdes Prog Serializer / Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9257GTL+T 功能描述:串行器/解串器 - Serdes Prog Serializer / Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9258 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Fully Programmable Serializer/Deserializer with UART/I2C Control Channel
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